diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index 50ea3ba837..6ba3e7de25 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -180,6 +180,7 @@ chip soc/intel/alderlake
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
+				.pcie_rp_detect_timeout_ms		= 50,
 			}"
 			smbios_slot_desc				"SlotTypePciExpressGen3X4"
 									"SlotLengthLong"
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 3174a81c57..16603f3569 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -156,6 +156,7 @@ chip soc/intel/alderlake
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
+				.pcie_rp_detect_timeout_ms		= 50,
 			}"
 
 			smbios_slot_desc				"SlotTypeM2Socket3"