arch/x86: Move prologue to .init section

For arch/x86 the realmode part has to be located within the same 64
KiB as the reset vector. Some older intel platforms also require 4 KiB
alignment for _start16bit.

To enforce the above, and to separate required parts of .text without
matching *(.text.*) rules in linker scripts, tag the pre-C environment
assembly code with section .init directive.

Description of .init section for ELF:

This section holds executable instructions that contribute to the
process initialization code. When a program starts to run, the
system arranges to execute the code in this section before calling the
main program entry point (called main for C programs).

Change-Id: If32518b1c19d08935727330314904b52a246af3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/car/core2/cache_as_ram.S

@@ -4,6 +4,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 
+.section .init
 .global bootblock_pre_c_entry
 
 .code32

src/cpu/intel/car/non-evict/cache_as_ram.S

@@ -7,6 +7,7 @@
 #define NoEvictMod_MSR 0x2e0
 #define BBL_CR_CTL3_MSR 0x11e
 
+.section .init
 .global bootblock_pre_c_entry
 
 #include <cpu/intel/car/cache_as_ram_symbols.inc>

src/cpu/intel/car/p3/cache_as_ram.S

@@ -4,6 +4,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 
+.section .init
 .global bootblock_pre_c_entry
 
 .code32

src/cpu/intel/car/p4-netburst/cache_as_ram.S

@@ -8,6 +8,7 @@
 /* Macro to access Local APIC registers at default base. */
 #define LAPIC(x)		$(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
 
+.section .init
 .global bootblock_pre_c_entry
 
 .code32

src/cpu/intel/microcode/microcode_asm.S

@@ -44,7 +44,7 @@
  */
 
 .code32
-.section .text
+.section .init
 .global update_bsp_microcode
 
 update_bsp_microcode: