From 7521f3ea830d814bca062ac11037fbca47e9cc42 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 18 Nov 2025 17:35:10 +0000 Subject: [PATCH] soc/qualcomm/x1p42100: Define pre and post-RAM DMA coherent regions This commit updates the linker script to properly define and name the DMA coherent memory regions used before and after DRAM initialization. 1. Rename Pre-RAM DMA Region: The existing `DMA_COHERENT` region allocated in BSRAM at `0x14857000` is renamed to `PRERAM_DMA_COHERENT`. This aligns the linker script with the code changes (in `mmu.c`) which use the more specific name for the early boot DMA buffer. 2. Add Post-RAM DMA Region: A new region, `POSTRAM_DMA_COHERENT`, is defined at the very start of DRAM (`0x80000000`) with an 8KB size. This region is intended for general-purpose DMA operations that occur after DRAM is active, ensuring a reserved, known, and uncached region for peripherals. The memory map diagram comments are also updated to reflect these new region names. BUG=b:456953373 TEST=Able to build and boot google/quenbi. Change-Id: I6fb4b9bf3425b311169ac43e1997f6574b571e00 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/90098 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/x1p42100/memlayout.ld | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld index 5bf877e616..c93ed62462 100644 --- a/src/soc/qualcomm/x1p42100/memlayout.ld +++ b/src/soc/qualcomm/x1p42100/memlayout.ld @@ -81,7 +81,7 @@ * 0x80E00000 +----------------------------------------------------------+ | | * | dram_ncc | | | * 0x80A00000 +----------------------------------------------------------+ | | - * | ... Usable memory ... | v v + * | postram_dma_coherent_dram | v v * 0x80000000 +----------------------------------------------------------+ <-------------- * | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX * 0x24060000 +----------------------------------------------------------+ <--------- @@ -127,7 +127,7 @@ * 0x1485B000 +----------------------------------------------------------+ | * | ... Usable memory ... | | * 0x14859000 +----------------------------------------------------------+ | - * | DMA_COHERENT | | + * | preram_dma_coherent_dram | | * 0x14857000 +----------------------------------------------------------+ | * | VBOOT2_WORK | | * 0x14854000 +----------------------------------------------------------+ | @@ -194,7 +194,7 @@ SECTIONS TIMESTAMP(0x14841C00, 1K) TTB(0x14842000, 56K) VBOOT2_WORK(0x14854000, 12K) - DMA_COHERENT(0x14857000, 8K) + PRERAM_DMA_COHERENT(0x14857000, 8K) REGION(qclib_serial_log, 0x1485B000, 4K, 4K) CBFS_MCACHE(0x1485C000,16K) FMAP_CACHE(0x14860400, 2K) @@ -214,6 +214,7 @@ SECTIONS REGION(shrm, 0x24040000, 128K , 4K) DRAM_START(0x80000000) + POSTRAM_DMA_COHERENT(0x80000000, 8K) REGION(dram_ncc, 0x80A00000, 0x400000, 4K) REGION(dram_cpucp, 0x80E00000, 0x7A0000, 4K)