From 74e7b3a0ea86b09b33a68703845c1001ac1514b5 Mon Sep 17 00:00:00 2001 From: Ingo Reitz <9l@9lo.re> Date: Thu, 16 Jan 2025 22:42:12 +0100 Subject: [PATCH] mb/google/volteer/variants/drobit: fix power_limits_config Drobit shows little power usage (around 9W) and very low clock speeds (1.1GHz - 1.4GHz) under load (`stress -c $(nproc)`), despite being at temperature too low for thermal throttling (40-50C). It turns out that power_limits_config is set to the lower end of the dptf power limit ranges as opposed to baseboard and other variants. This seems to prevent the device from using the intended power limits. Tested: Boot and confirm more reasoable power usage (17W) and clock speeds (around 2.5GHz) as well as good temperatures (topped 85C) and stability under 100% load (`stress -c $(nproc)` for 30min). Device for tests is i5-1135G7 and 16GG RAM. Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b Signed-off-by: Ingo Reitz <9l@9lo.re> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86026 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/drobit/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index c791079c61..148af6e66f 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -12,8 +12,8 @@ chip soc/intel/tigerlake register "tcc_offset" = "8" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 9, - .tdp_pl2_override = 28, + .tdp_pl1_override = 17, + .tdp_pl2_override = 64, .tdp_pl4 = 105, }"