diff --git a/src/soc/nvidia/tegra124/clk_rst.h b/src/soc/nvidia/tegra124/clk_rst.h
index 156e9a69fa..394b1d9353 100644
--- a/src/soc/nvidia/tegra124/clk_rst.h
+++ b/src/soc/nvidia/tegra124/clk_rst.h
@@ -525,4 +525,15 @@ enum {
 	CRC_RST_CPUG_CLR_PDBG = 0x1 << 30,
 };
 
+// RST_CPULP_CMPLX_CLR
+enum {
+	CRC_RST_CPULP_CLR_CPU0 = 0x1 << 0,
+	CRC_RST_CPULP_CLR_DBG0 = 0x1 << 12,
+	CRC_RST_CPULP_CLR_CORE0 = 0x1 << 16,
+	CRC_RST_CPULP_CLR_CX0 = 0x1 << 20,
+	CRC_RST_CPULP_CLR_L2 = 0x1 << 24,
+	CRC_RST_CPULP_CLR_NONCPU = 0x1 << 29,
+	CRC_RST_CPULP_CLR_PDBG = 0x1 << 30,
+};
+
 #endif	/* _TEGRA124_CLK_RST_H_ */
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index 26e25f963b..cb65334736 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -357,6 +357,7 @@ void clock_cpu0_config_and_reset(void *entry)
 	// Enable other CPU related clocks.
 	setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU);
 	setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG);
+	setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP);
 
 	// Disable the reset on the non-CPU parts of the fast cluster.
 	write32(CRC_RST_CPUG_CLR_NONCPU,
@@ -372,6 +373,15 @@ void clock_cpu0_config_and_reset(void *entry)
 		CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 |
 		CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
 		&clk_rst->rst_cpug_cmplx_clr);
+
+	// Disable the reset on the non-CPU parts of the slow cluster.
+	write32(CRC_RST_CPULP_CLR_NONCPU,
+		&clk_rst->rst_cpulp_cmplx_clr);
+	// Disable the various resets on the LP CPU.
+	write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 |
+		CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 |
+		CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG,
+		&clk_rst->rst_cpulp_cmplx_clr);
 }
 
 void clock_halt_avp(void)