diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v3.h b/src/soc/mediatek/common/include/soc/dsi_register_v3.h
new file mode 100644
index 0000000000..f0bd0a9f52
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/dsi_register_v3.h
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DSI_REGISTER_V3_H
+#define DSI_REGISTER_V3_H
+
+#include <commonlib/helpers.h>
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct dsi_regs {
+	u32 dsi_start;
+	u32 dsi_status;
+	u32 dsi_inten;
+	u32 dsi_intsta;
+	u32 dsi_dp_inten;
+	u32 dsi_dp_intsta;
+	u32 dsi_scp_inten;
+	u32 dsi_scp_intsta;
+	u32 dsi_cg_con;
+	u32 dsi_rst_con;
+	u32 dsi_1tnp_con;
+	u32 dsi_size_con;
+	u32 dsi_con_ctrl;
+	u32 dsi_mode_ctrl;
+	u32 dsi_txrx_ctrl;
+	u32 dsi_psctrl;
+	u32 dsi_v3d_con;
+	u32 dsi_cmdq_size;
+	u32 dsi_mem_conti;
+	u32 dsi_frm_bc;
+	u32 dsi_cmd_type1_hs;
+	u32 dsi_cmd_type1_lp_ext;
+	u32 dsi_ext_source;
+	u32 reserved0;
+	u32 dsi_vsa_nl;
+	u32 dsi_vbp_nl;
+	u32 dsi_vfp_nl;
+	u32 dsi_vact_nl;
+	u32 reserved1[4];
+	u32 dsi_hsa_wc;
+	u32 dsi_hbp_wc;
+	u32 dsi_hfp_wc;
+	u32 dsi_bllp_wc;
+	u32 reserved2[4];
+	u32 dsi_rx_con;
+	u32 dsi_rx_data03;
+	u32 dsi_rx_data47;
+	u32 dsi_rx_data8b;
+	u32 dsi_rx_datac;
+	u32 dsi_rx_rack;
+	u32 dsi_rx_trig_sta;
+	u32 reserved3;
+	u32 dsi_dma_in_con0;
+	u32 dsi_dma_in_con1;
+	u32 reserved4[2];
+	u32 dsi_shadow_ctrl;
+	u32 dsi_shadow_group_en;
+	u32 dsi_shadow_source_sel;
+	u32 dsi_shadow_sta;
+	u32 reserved5[4];
+	u32 dsi_target_nl;
+	u32 reserved6;
+	u32 dsi_scramble_con;
+	u32 reserved7;
+	u32 dsi_hstx_cklp_wc;
+	u32 dsi_hstx_cklp_wc_auto_result;
+	u32 reserved8[2];
+	u32 dsi_vm_cmd_con;
+	u32 dsi_vm_cmd_con1;
+	u32 dsi_vm_cmd_data[16];
+	u32 reserved9[6];
+	u32 dsi_vfp_early_stop;
+	u32 dsi_vfp_early_stop_interval;
+	u32 dsi_vfp_early_stop_l0;
+	u32 dsi_vfp_early_stop_l2;
+	u32 dsi_vfp_early_stop_l4;
+	u32 dsi_vfp_early_stop_l6;
+	u32 reserved10[2];
+	u32 dsi_em_gen_con;
+	u32 reserved11[3];
+	u32 dsi_lfr_con;	/* Available since MT8183 */
+	u32 dsi_lfr_sta;	/* Available since MT8183 */
+	u32 dsi_ltpo_vdo_con;
+	u32 dsi_ltpo_vdo_sq0;
+	u32 dsi_ltpo_vdo_sq1;
+	u32 dsi_ltpo_vdo_sq2;
+	u32 dsi_ltpo_vdo_sq3;
+	u32 dsi_ltpo_vdo_sq4;
+	u32 reserved12[4];
+	u32 dsi_phy_lccon;
+	u32 dsi_phy_ld0con;
+	u32 dsi_phy_syncon;
+	u32 reserved13;
+	u32 dsi_cphy_con0;
+	u32 dsi_cphy_con1;
+	u32 reserved14[6];
+	u32 dsi_time_con0;
+	u32 dsi_time_con1;
+	u32 dsi_time_con2;
+	u32 reserved15;
+	u32 dsi_gce_event_con0;
+	u32 dsi_gce_event_con1;
+	u32 reserved16[2];
+	u32 dsi_dbg_con0;
+	u32 dsi_dbg_con1;
+	u32 reserved17[2];
+	u32 dsi_self_pat_con0;
+	u32 dsi_self_pat_con1;
+	u32 reserved18[2];
+	u32 dsi_input_setting;
+	u32 dsi_input_debug;
+	u32 dsi_in_cksm;
+	u32 reserved19;
+	u32 dsi_cksm_out;
+	u32 dsi_crc_cksm;
+	u32 dsi_sof_num;
+	u32 reserved20;
+	u32 dsi_frame_cnt_dsick;
+	u32 dsi_frame_cnt_mmck;
+	u32 reserved21[2];
+	u32 dsi_mac_state_dbg0[5];
+	u32 reserved22[7];
+	u32 dsi_mute_mode_con;
+	u32 dsi_mute_mode_dbg;
+	u32 reserved23[22];
+	u32 dsi_buf_con0;
+	u32 dsi_buf_con1;
+	u32 dsi_buf_reset;
+	u32 dsi_buf_log;
+	u32 dsi_buf_rw_times;
+	u32 dsi_buf_sodi_high;
+	u32 dsi_buf_sodi_low;
+	u32 dsi_buf_dvfs_high;
+	u32 dsi_buf_dvfs_low;
+	u32 dsi_buf_preultra_high;
+	u32 dsi_buf_preultra_low;
+	u32 dsi_buf_ultra_high;
+	u32 dsi_buf_ultra_low;
+	u32 dsi_buf_urgent_high;
+	u32 dsi_buf_urgent_low;
+	u32 dsi_buf_preurgent_high;
+	u32 reserved24[32];
+	u32 dsi_ocla_con0;
+	u32 reserved25;
+	u32 dsi_ocla_sub_log[5];
+	u32 dsi_ocla_dsi_log[5];
+	u32 dsi_mac_err;
+	u32 dsi_rollback_dbg;
+	u32 dsi_reserved;
+	u32 dsi_reserved_w_shadow;
+	u32 dsi_cmdq[128];
+	u32 dsi_phy_timecon0;
+	u32 dsi_phy_timecon1;
+	u32 dsi_phy_timecon2;
+	u32 dsi_phy_timecon3;
+	u32 dsi_phy_lcpat;
+	u32 dsi_phy_con;
+	u32 dsi_dphy_lane_swap;
+	u32 dsi_cphy_trio_swap;
+	u32 reserved26[2];
+	u32 dsi_cphy_trio_con;
+	u32 reserved27;
+	u32 dsi_dphy_dbg0;
+	u32 dsi_dphy_dbg1;
+	u32 dsi_dphy_dbg2;
+	u32 dsi_dphy_dbg3;
+	u32 dsi_dphy_dbg4;
+	u32 dsi_dphy_dbg5;
+	u32 dsi_dphy_dbg6;
+	u32 reserved28;
+	u32 dsi_cphy_dbg0;
+	u32 dsi_cphy_dbg1;
+	u32 reserved29[2];
+	u32 dsi_phy_dbg_con;
+	u32 reserved30[8];
+	u32 dsi_line_time_fix;
+	u32 reserved31[2];
+	u32 dsi_phy_cg_con;
+	u32 reserved32[26];
+	u32 dsi_phy_rollback_dbg;
+};
+
+check_member(dsi_regs, dsi_buf_con0, 0x300);
+check_member(dsi_regs, dsi_ocla_con0, 0x3C0);
+check_member(dsi_regs, dsi_phy_timecon0, 0x600);
+check_member(dsi_regs, dsi_phy_cg_con, 0x690);
+check_member(dsi_regs, dsi_phy_rollback_dbg, 0x6FC);
+
+static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
+static struct dsi_regs *const dsi1 = (void *)DSI1_BASE;
+
+#endif /* DSI_REGISTER_V3_H */
diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h
index dd16892646..b7b5ef8027 100644
--- a/src/soc/mediatek/mt8196/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h
@@ -76,8 +76,9 @@ enum {
 	IOCFG_LM1_BASE		= IO_PHYS + 0x03020000,
 	IOCFG_LM2_BASE		= IO_PHYS + 0x03040000,
 	EDP_PHY_BASE		= IO_PHYS + 0x030A0000,
-	MIPITX0_BASE		= IO_PHYS + 0x030b0000,
-	IOCFG_LB1_BASE		= IO_PHYS + 0x030f0000,
+	MIPITX0_BASE		= IO_PHYS + 0x030B0000,
+	MIPITX1_BASE		= IO_PHYS + 0x030C0000,
+	IOCFG_LB1_BASE		= IO_PHYS + 0x030F0000,
 	IOCFG_LB2_BASE		= IO_PHYS + 0x03110000,
 	I2C0_BASE		= IO_PHYS + 0x03130000,
 	I2C3_BASE		= IO_PHYS + 0x03150000,
@@ -214,6 +215,7 @@ enum {
 	DSC2_BASE		= IO_PHYS + 0x22470000,
 	DSC3_BASE		= IO_PHYS + 0x22480000,
 	DSI0_BASE		= IO_PHYS + 0x22490000,
+	DSI1_BASE		= IO_PHYS + 0x224A0000,
 	DISP_DVO0		= IO_PHYS + 0x224C0000,
 	OVLSYS_CONFIG_BASE	= IO_PHYS + 0x22800000,
 	OVLSYS_MUTEX_BASE	= IO_PHYS + 0x22820000,
diff --git a/src/soc/mediatek/mt8196/include/soc/dsi.h b/src/soc/mediatek/mt8196/include/soc/dsi.h
index 07278c2532..f9021346f4 100644
--- a/src/soc/mediatek/mt8196/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8196/include/soc/dsi.h
@@ -4,5 +4,12 @@
 #define SOC_MEDIATEK_MT8196_DSI_H
 
 #include <soc/dsi_common.h>
+#include <soc/dsi_reg.h>
+
+#define MTK_DSI_MIPI_RATIO_NUMERATOR	100
+#define MTK_DSI_MIPI_RATIO_DENOMINATOR	100
+#define MTK_DSI_DATA_RATE_MIN_MHZ	125
+#define MTK_DSI_HAVE_SIZE_CON		1
+#define PIXEL_STREAM_CUSTOM_HEADER	0xb
 
 #endif
diff --git a/src/soc/mediatek/mt8196/include/soc/dsi_reg.h b/src/soc/mediatek/mt8196/include/soc/dsi_reg.h
new file mode 100644
index 0000000000..05460ff167
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/dsi_reg.h
@@ -0,0 +1,506 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8196_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8196_DSI_REG_H_
+
+#include <commonlib/helpers.h>
+#include <soc/addressmap.h>
+#include <soc/dsi_register_v3.h>
+#include <types.h>
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 reserved0;
+	u32 lane_con;
+	u32 voltage_sel;
+	u32 cdphy_preserved;
+	u32 dphy_lane_con;
+	u32 dphy_voltage_sel;
+	u32 dphy_preserved;
+	u32 test_con;
+	u32 top_con;
+	u32 ser_data;
+	u32 pll_pwr;
+	u32 pll_con0;
+	u32 pll_con1;
+	u32 pll_con2;
+	u32 pll_con3;
+	u32 pll_con4;
+	u32 phy_sel0;
+	u32 pa_con;
+	u32 ser_data1;
+	u32 ser_con;
+	u32 sw_ctrl_con4;
+	u32 gpio_con;
+	u32 dbg_con;
+	u32 err_sta;
+	u32 in_mux_sel;
+	u32 vidle_con;
+	u32 vidle_trig;
+	u32 vidle_timing_con0;
+	u32 vidle_timing_con1;
+	u32 vidle_dbg_sta0;
+	u32 vidle_dbg_sta1;
+	u32 vidle_cap_addr0;
+	u32 vidle_cap_addr1;
+	u32 vidle_cap_data0;
+	u32 vidle_cap_data1;
+	u32 vidle_cap_data2;
+	u32 vidle_cap_data3;
+	u32 reserved1[27];
+	u32 d2p_rtcode3_0;
+	u32 d2p_rtcode4;
+	u32 d2n_rtcode3_0;
+	u32 d2n_rtcode4;
+	u32 d2p_skew_hi;
+	u32 d2p_skew_lo;
+	u32 d2n_skew_hi;
+	u32 d2n_skew_lo;
+	u32 d2_ckmode_en;
+	u32 d2_ana_pn_swap_en;
+	u32 d2_t0_tiel_en;
+	u32 d2_ser_bisttog;
+	u32 d2_ser_din_sel;
+	u32 d2_ldoout_en;
+	u32 d2_loopback_en;
+	u32 d2_lptx_iplus1;
+	u32 d2_lptx_iplus2;
+	u32 d2_lptx_iminus;
+	u32 d2_lpcd_iplus;
+	u32 d2_lpcd_iminus;
+	u32 d2_rtcode;
+	u32 d2_cklane_en;
+	u32 d2_dig_pn_swap_en;
+	u32 d2_sw_ctl_en;
+	u32 d2_sw_lptx_pre_oe;
+	u32 d2_sw_lptx_oe;
+	u32 d2_sw_lptx_dp;
+	u32 d2_sw_lptx_dn;
+	u32 d2_sw_lprx_en;
+	u32 d2_sw_hstx_pre_oe;
+	u32 d2_sw_hstx_oe;
+	u32 d2_sw_hstx_rdy;
+	u32 d2c_sw_lptx_pre_oe;
+	u32 d2c_sw_lptx_oe;
+	u32 d2c_sw_lprx_en;
+	u32 d2c_sw_hstx_pre_oe;
+	u32 d2c_sw_hstx_oe;
+	u32 d2c_sw_hstx_rdy;
+	u32 d2_sw_hstx_data1_0;
+	u32 d2_sw_hstx_data3_2;
+	u32 d2_sw_hstx_data5_4;
+	u32 d2_sw_hstx_data7_6;
+	u32 d2c_sw_hstx_data1_0;
+	u32 d2c_sw_hstx_data3_2;
+	u32 d2c_sw_hstx_data5_4;
+	u32 d2c_sw_hstx_data6;
+	u32 d2_sw_cd_con;
+	u32 d2_ad_rx;
+	u32 d2_ad_cd;
+	u32 d2p_rt_dem_code;
+	u32 d2n_rt_dem_code;
+	u32 d2_hstx_ldo_iboost_en;
+	u32 d2_dbg_sel;
+	u32 d2_chksum0;
+	u32 d2_chksum1;
+	u32 d2_chksum2;
+	u32 d2_chksum3;
+	u32 d2_chksum4;
+	u32 d2_chksum5;
+	u32 d2_phy_rst_sel;
+	u32 d2c_abc_swap_sel;
+	u32 reserved2[3];
+	u32 d0p_rtcode3_0;
+	u32 d0p_rtcode4;
+	u32 d0n_rtcode3_0;
+	u32 d0n_rtcode4;
+	u32 d0p_skew_hi;
+	u32 d0p_skew_lo;
+	u32 d0n_skew_hi;
+	u32 d0n_skew_lo;
+	u32 d0_ckmode_en;
+	u32 d0_ana_pn_swap_en;
+	u32 d0_t0_tiel_en;
+	u32 d0_ser_bisttog;
+	u32 d0_ser_din_sel;
+	u32 d0_ldoout_en;
+	u32 d0_loopback_en;
+	u32 d0_lptx_iplus1;
+	u32 d0_lptx_iplus2;
+	u32 d0_lptx_iminus;
+	u32 d0_lpcd_iplus;
+	u32 d0_lpcd_iminus;
+	u32 d0_rtcode;
+	u32 d0_cklane_en;
+	u32 d0_dig_pn_swap_en;
+	u32 d0_sw_ctl_en;
+	u32 d0_sw_lptx_pre_oe;
+	u32 d0_sw_lptx_oe;
+	u32 d0_sw_lptx_dp;
+	u32 d0_sw_lptx_dn;
+	u32 d0_sw_lprx_en;
+	u32 d0_sw_hstx_pre_oe;
+	u32 d0_sw_hstx_oe;
+	u32 d0_sw_hstx_rdy;
+	u32 d0c_sw_lptx_pre_oe;
+	u32 d0c_sw_lptx_oe;
+	u32 d0c_sw_lprx_en;
+	u32 d0c_sw_hstx_pre_oe;
+	u32 d0c_sw_hstx_oe;
+	u32 d0c_sw_hstx_rdy;
+	u32 d0_sw_hstx_data1_0;
+	u32 d0_sw_hstx_data3_2;
+	u32 d0_sw_hstx_data5_4;
+	u32 d0_sw_hstx_data7_6;
+	u32 d0c_sw_hstx_data1_0;
+	u32 d0c_sw_hstx_data3_2;
+	u32 d0c_sw_hstx_data5_4;
+	u32 d0c_sw_hstx_data6;
+	u32 d0_sw_cd_con;
+	u32 d0_ad_rx;
+	u32 d0_ad_cd;
+	u32 d0p_rt_dem_code;
+	u32 d0n_rt_dem_code;
+	u32 d0_hstx_ldo_iboost_en;
+	u32 d0_dbg_sel;
+	u32 d0_chksum0;
+	u32 d0_chksum1;
+	u32 d0_chksum2;
+	u32 d0_chksum3;
+	u32 d0_chksum4;
+	u32 d0_chksum5;
+	u32 d0_phy_rst_sel;
+	u32 d0c_abc_swap_sel;
+	u32 reserved3[3];
+	u32 ckp_rtcode3_0;
+	u32 ckp_rtcode4;
+	u32 ckn_rtcode3_0;
+	u32 ckn_rtcode4;
+	u32 ckp_skew_hi;
+	u32 ckp_skew_lo;
+	u32 ckn_skew_hi;
+	u32 ckn_skew_lo;
+	u32 ck_ckmode_en;
+	u32 ck_ana_pn_swap_en;
+	u32 ck_t0_tiel_en;
+	u32 ck_ser_bisttog;
+	u32 ck_ser_din_sel;
+	u32 ck_ldoout_en;
+	u32 ck_loopback_en;
+	u32 ck_lptx_iplus1;
+	u32 ck_lptx_iplus2;
+	u32 ck_lptx_iminus;
+	u32 ck_lpcd_iplus;
+	u32 ck_lpcd_iminus;
+	u32 ck_rtcode;
+	u32 ck_cklane_en;
+	u32 ck_dig_pn_swap_en;
+	u32 ck_sw_ctl_en;
+	u32 ck_sw_lptx_pre_oe;
+	u32 ck_sw_lptx_oe;
+	u32 ck_sw_lptx_dp;
+	u32 ck_sw_lptx_dn;
+	u32 ck_sw_lprx_en;
+	u32 ck_sw_hstx_pre_oe;
+	u32 ck_sw_hstx_oe;
+	u32 ck_sw_hstx_rdy;
+	u32 ckc_sw_lptx_pre_oe;
+	u32 ckc_sw_lptx_oe;
+	u32 ckc_sw_lprx_en;
+	u32 ckc_sw_hstx_pre_oe;
+	u32 ckc_sw_hstx_oe;
+	u32 ckc_sw_hstx_rdy;
+	u32 ck_sw_hstx_data1_0;
+	u32 ck_sw_hstx_data3_2;
+	u32 ck_sw_hstx_data5_4;
+	u32 ck_sw_hstx_data7_6;
+	u32 ckc_sw_hstx_data1_0;
+	u32 ckc_sw_hstx_data3_2;
+	u32 ckc_sw_hstx_data5_4;
+	u32 ckc_sw_hstx_data6;
+	u32 ck_sw_cd_con;
+	u32 ck_ad_rx;
+	u32 ck_ad_cd;
+	u32 ckp_rt_dem_code;
+	u32 ckn_rt_dem_code;
+	u32 ck_hstx_ldo_iboost_en;
+	u32 ck_dbg_sel;
+	u32 ck_chksum0;
+	u32 ck_chksum1;
+	u32 ck_chksum2;
+	u32 ck_chksum3;
+	u32 ck_chksum4;
+	u32 ck_chksum5;
+	u32 ck_phy_rst_sel;
+	u32 ckc_abc_swap_sel;
+	u32 reserved4[3];
+	u32 d1p_rtcode3_0;
+	u32 d1p_rtcode4;
+	u32 d1n_rtcode3_0;
+	u32 d1n_rtcode4;
+	u32 d1p_skew_hi;
+	u32 d1p_skew_lo;
+	u32 d1n_skew_hi;
+	u32 d1n_skew_lo;
+	u32 d1_ckmode_en;
+	u32 d1_ana_pn_swap_en;
+	u32 d1_t0_tiel_en;
+	u32 d1_ser_bisttog;
+	u32 d1_ser_din_sel;
+	u32 d1_ldoout_en;
+	u32 d1_loopback_en;
+	u32 d1_lptx_iplus1;
+	u32 d1_lptx_iplus2;
+	u32 d1_lptx_iminus;
+	u32 d1_lpcd_iplus;
+	u32 d1_lpcd_iminus;
+	u32 d1_rtcode;
+	u32 d1_cklane_en;
+	u32 d1_dig_pn_swap_en;
+	u32 d1_sw_ctl_en;
+	u32 d1_sw_lptx_pre_oe;
+	u32 d1_sw_lptx_oe;
+	u32 d1_sw_lptx_dp;
+	u32 d1_sw_lptx_dn;
+	u32 d1_sw_lprx_en;
+	u32 d1_sw_hstx_pre_oe;
+	u32 d1_sw_hstx_oe;
+	u32 d1_sw_hstx_rdy;
+	u32 d1c_sw_lptx_pre_oe;
+	u32 d1c_sw_lptx_oe;
+	u32 d1c_sw_lprx_en;
+	u32 d1c_sw_hstx_pre_oe;
+	u32 d1c_sw_hstx_oe;
+	u32 d1c_sw_hstx_rdy;
+	u32 d1_sw_hstx_data1_0;
+	u32 d1_sw_hstx_data3_2;
+	u32 d1_sw_hstx_data5_4;
+	u32 d1_sw_hstx_data7_6;
+	u32 d1c_sw_hstx_data1_0;
+	u32 d1c_sw_hstx_data3_2;
+	u32 d1c_sw_hstx_data5_4;
+	u32 d1c_sw_hstx_data6;
+	u32 d1_sw_cd_con;
+	u32 d1_ad_rx;
+	u32 d1_ad_cd;
+	u32 d1p_rt_dem_code;
+	u32 d1n_rt_dem_code;
+	u32 d1_hstx_ldo_iboost_en;
+	u32 d1_dbg_sel;
+	u32 d1_chksum0;
+	u32 d1_chksum1;
+	u32 d1_chksum2;
+	u32 d1_chksum3;
+	u32 d1_chksum4;
+	u32 d1_chksum5;
+	u32 d1_phy_rst_sel;
+	u32 d1c_abc_swap_sel;
+	u32 reserved5[3];
+	u32 d3p_rtcode3_0;
+	u32 d3p_rtcode4;
+	u32 d3n_rtcode3_0;
+	u32 d3n_rtcode4;
+	u32 d3p_skew_hi;
+	u32 d3p_skew_lo;
+	u32 d3n_skew_hi;
+	u32 d3n_skew_lo;
+	u32 d3_ckmode_en;
+	u32 d3_ana_pn_swap_en;
+	u32 d3_t0_tiel_en;
+	u32 d3_ser_bisttog;
+	u32 d3_ser_din_sel;
+	u32 d3_ldoout_en;
+	u32 d3_loopback_en;
+	u32 d3_lptx_iplus1;
+	u32 d3_lptx_iplus2;
+	u32 d3_lptx_iminus;
+	u32 d3_lpcd_iplus;
+	u32 d3_lpcd_iminus;
+	u32 d3_rtcode;
+	u32 d3_cklane_en;
+	u32 d3_dig_pn_swap_en;
+	u32 d3_sw_ctl_en;
+	u32 d3_sw_lptx_pre_oe;
+	u32 d3_sw_lptx_oe;
+	u32 d3_sw_lptx_dp;
+	u32 d3_sw_lptx_dn;
+	u32 d3_sw_lprx_en;
+	u32 d3_sw_hstx_pre_oe;
+	u32 d3_sw_hstx_oe;
+	u32 d3_sw_hstx_rdy;
+	u32 d3c_sw_lptx_pre_oe;
+	u32 d3c_sw_lptx_oe;
+	u32 d3c_sw_lprx_en;
+	u32 d3c_sw_hstx_pre_oe;
+	u32 d3c_sw_hstx_oe;
+	u32 d3c_sw_hstx_rdy;
+	u32 d3_sw_hstx_data1_0;
+	u32 d3_sw_hstx_data3_2;
+	u32 d3_sw_hstx_data5_4;
+	u32 d3_sw_hstx_data7_6;
+	u32 d3c_sw_hstx_data1_0;
+	u32 d3c_sw_hstx_data3_2;
+	u32 d3c_sw_hstx_data5_4;
+	u32 d3c_sw_hstx_data6;
+	u32 d3_sw_cd_con;
+	u32 d3_ad_rx;
+	u32 d3_ad_cd;
+	u32 d3p_rt_dem_code;
+	u32 d3n_rt_dem_code;
+	u32 d3_hstx_ldo_iboost_en;
+	u32 d3_dbg_sel;
+	u32 d3_chksum0;
+	u32 d3_chksum1;
+	u32 d3_chksum2;
+	u32 d3_chksum3;
+	u32 d3_chksum4;
+	u32 d3_chksum5;
+	u32 d3_phy_rst_sel;
+	u32 d3c_abc_swap_sel;
+	u32 reserved6[3];
+	u32 dphy_bist_con0;
+	u32 dphy_bist_con1;
+	u32 dphy_bist_con2;
+	u32 reserved7[2];
+	u32 dphy_bist_pattern_0;
+	u32 dphy_bist_pattern_1;
+	u32 dphy_bist_pattern_2;
+	u32 dphy_bist_pattern_3;
+	u32 dphy_bist_pattern_4;
+	u32 dphy_bist_pattern_5;
+	u32 dphy_bist_pattern_6;
+	u32 dphy_bist_pattern_7;
+	u32 cphy_bist_con0;
+	u32 cphy_bist_con1;
+	u32 cphy_bist_wire_state;
+	u32 cphy_bist_prb_sel;
+	u32 reserved8[4];
+	u32 cphy_bist_progseq_lsb_0;
+	u32 cphy_bist_progseq_lsb_1;
+	u32 cphy_bist_progseq_lsb_2;
+	u32 cphy_bist_progseq_lsb_3;
+	u32 cphy_bist_progseq_lsb_4;
+	u32 cphy_bist_progseq_lsb_5;
+	u32 cphy_bist_progseq_lsb_6;
+	u32 cphy_bist_progseq_lsb_7;
+	u32 cphy_bist_progseq_msb_0;
+	u32 cphy_bist_progseq_msb_1;
+	u32 cphy_bist_progseq_msb_2;
+	u32 cphy_bist_prb_seed_0;
+	u32 cphy_bist_prb_seed_1;
+	u32 cphy_bist_prb_seed_2;
+	u32 cphy_bist_prb_seed_3;
+	u32 cphy_bist_prb_seed_4;
+	u32 cphy_bist_prebegin_sym;
+	u32 cphy_bist_preend_sym;
+	u32 reserved9;
+	u32 bist_timing00_hi;
+	u32 bist_timing00_lo;
+	u32 bist_timing01_hi;
+	u32 bist_timing01_lo;
+	u32 bist_timing02_hi;
+	u32 bist_timing02_lo;
+	u32 bist_timing03_hi;
+	u32 bist_timing03_lo;
+	u32 bist_timing04_hi;
+	u32 bist_timing04_lo;
+	u32 bist_timing05_hi;
+	u32 bist_timing05_lo;
+	u32 bist_timing06_hi;
+	u32 bist_timing06_lo;
+	u32 bist_timing07_hi;
+	u32 bist_timing07_lo;
+	u32 bist_timing08_hi;
+	u32 bist_timing08_lo;
+	u32 bist_timing09_hi;
+	u32 bist_timing09_lo;
+	u32 bist_timing10_hi;
+	u32 bist_timing10_lo;
+	u32 reserved10[2];
+	u32 ck1p_rtcode3_0;
+	u32 ck1p_rtcode4;
+	u32 ck1n_rtcode3_0;
+	u32 ck1n_rtcode4;
+	u32 ck1p_skew_hi;
+	u32 ck1p_skew_lo;
+	u32 ck1n_skew_hi;
+	u32 ck1n_skew_lo;
+	u32 ck1_ckmode_en;
+	u32 ck1_ana_pn_swap_en;
+	u32 ck1_t0_tiel_en;
+	u32 ck1_ser_bisttog;
+	u32 ck1_ser_din_sel;
+	u32 ck1_ldoout_en;
+	u32 ck1_loopback_en;
+	u32 ck1_lptx_iplus1;
+	u32 ck1_lptx_iplus2;
+	u32 ck1_lptx_iminus;
+	u32 ck1_lpcd_iplus;
+	u32 ck1_lpcd_iminus;
+	u32 ck1_rtcode;
+	u32 ck1_cklane_en;
+	u32 ck1_dig_pn_swap_en;
+	u32 ck1_sw_ctl_en;
+	u32 ck1_sw_lptx_pre_oe;
+	u32 ck1_sw_lptx_oe;
+	u32 ck1_sw_lptx_dp;
+	u32 ck1_sw_lptx_dn;
+	u32 ck1_sw_lprx_en;
+	u32 ck1_sw_hstx_pre_oe;
+	u32 ck1_sw_hstx_oe;
+	u32 ck1_sw_hstx_rdy;
+	u32 ck1c_sw_lptx_pre_oe;
+	u32 ck1c_sw_lptx_oe;
+	u32 ck1c_sw_lprx_en;
+	u32 ck1c_sw_hstx_pre_oe;
+	u32 ck1c_sw_hstx_oe;
+	u32 ck1c_sw_hstx_rdy;
+	u32 ck1_sw_hstx_data1_0;
+	u32 ck1_sw_hstx_data3_2;
+	u32 ck1_sw_hstx_data5_4;
+	u32 ck1_sw_hstx_data7_6;
+	u32 ck1c_sw_hstx_data1_0;
+	u32 ck1c_sw_hstx_data3_2;
+	u32 ck1c_sw_hstx_data5_4;
+	u32 ck1c_sw_hstx_data6;
+	u32 ck1_sw_cd_con;
+	u32 ck1_ad_rx;
+	u32 ck1_ad_cd;
+	u32 ck1p_rt_dem_code;
+	u32 ck1n_rt_dem_code;
+	u32 ck1_hstx_ldo_iboost_en;
+	u32 ck1_dbg_sel;
+	u32 ck1_chksum0;
+	u32 ck1_chksum1;
+	u32 ck1_chksum2;
+	u32 ck1_chksum3;
+	u32 ck1_chksum4;
+	u32 ck1_chksum5;
+	u32 ck1_phy_rst_sel;
+	u32 ck1c_abc_swap_sel;
+};
+
+check_member(mipi_tx_regs, d2p_rtcode3_0, 0x100);
+check_member(mipi_tx_regs, d0c_abc_swap_sel, 0x2F0);
+check_member(mipi_tx_regs, ck1p_rtcode3_0, 0x700);
+check_member(mipi_tx_regs, ck1c_abc_swap_sel, 0x7F0);
+
+static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPITX0_BASE;
+static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPITX1_BASE;
+
+/* Register values */
+#define RG_DSI_HSTX_LDO_REF_SEL		GENMASK(9, 6)
+#define RG_DSI_PRD_REF_SEL		GENMASK(5, 0)
+#define RG_DSI_PRD_REF_MINI		0
+#define RG_DSI_PRD_REF_DEF		4
+#define RG_DSI_PRD_REF_MAX		7
+
+#define DSI_CK_CKMODE_EN	BIT(0)
+#define DSI_SW_CTL_EN		BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
+
+#define RG_DSI_PLL_EN		BIT(0)
+#define RG_DSI_PLL_POSDIV	GENMASK(10, 8)
+
+#endif /* _SOC_MEDIATEK_MT8196_DSI_REG_H_ */