mb/google/brya/var/trulo: Enable Charger participant in Passive Policy

Update the TSR1 target's source to CHARGER in Passive Policy.

BUG=b:378623372
TEST=Build and boot on Trulo board.
Verified the source for TSR1 is updated to  Charger in Passive Policy

Change-Id: I43db616fd48fc4659dcba359f17854e14adb6039
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Vidya Gopalakrishnan 2024-11-21 14:50:04 +05:30 committed by Subrata Banik
commit 73a1f02592

View file

@ -240,7 +240,7 @@ chip soc/intel/alderlake
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 70, 5000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
}"
@ -337,7 +337,7 @@ chip soc/intel/alderlake
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 70, 5000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
}"