From 736941b6a4b16e6c2bb8fb175689752a77971e7c Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Tue, 31 Dec 2024 09:02:14 -0800 Subject: [PATCH] soc/intel/meteorlake: Add doc reference for thunderbolt port number Document #640228 Meteor Lake - U/H and U Type4 Processor - 2.3 Device IDs - Table 8 "Other Device ID" IDs - Table 8 "Other Device ID" specifies that the first Thunderbolt PCIe root port number is 16. Change-Id: Ic394aa6795105ff613f30e8aa0ffa45500c6332a Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/85820 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/meteorlake/pcie_rp.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/meteorlake/pcie_rp.c b/src/soc/intel/meteorlake/pcie_rp.c index 7cfe3ed291..914520efbb 100644 --- a/src/soc/intel/meteorlake/pcie_rp.c +++ b/src/soc/intel/meteorlake/pcie_rp.c @@ -6,13 +6,15 @@ #include /* - * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe - * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's - * PCIe remapping logic can return correct index (0-based) + * Document #640228 Meteor Lake - U/H and U Type4 Processor - 2.3 Device IDs - Table 8 "Other + * Device ID" specifies that the first Thunderbolt PCIe root port number is 16. TBT's LCAP + * registers return port index which starts from 16 (usually for other PCIe root ports index + * starts from 1). Thus, keeping lcap_port_base 16 for TBT, so that coreboot's PCIe remapping + * logic can return a correct index (0-based). */ static const struct pcie_rp_group tbt_rp_groups[] = { - { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 }, + { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 16 }, { 0 } };