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mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING

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According to the analysis results, resetting the DSI DPHY to default
during a warm boot is needed if 'You are in developer mode' needs to be
displayed on the screen in a system using the MIPI-DSI panel.

DPHY_0_CLOCK_LANE_TIMING -- address:0x162180, size: 32 bits
[31]: CLK_PREPARE Override. 0:HW maintains, 1:SW overrides
[30..28]: CLK_PREPARE
[27]: CLK_ZERO Override. 0:HW maintains, 1:SW overrides
[23..20]: CLK_ZERO
[19]: CLK_PRE Override. 0:HW maintains, 1:SW overrides
[17..16]: CLK_PRE
[15]: CLK_POST Override. 0:HW maintains, 1:SW overrides
[10..8]: CLK_POST
[7]: CLK_TRAIL Override. 0:HW maintains, 1:SW overrides
[2..0]: CLK_TRAIL

BUG=b:397805262
TEST=Able to show 'You are in developer mode'

Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179
Signed-off-by: Gareth Yu <gareth.yu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Gareth Yu 2025-03-27 16:21:09 +08:00 • committed by Matt DeVillier
commit 730b2b506b
2 changed files with 57 additions and 0 deletions
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1
src/mainboard/google/brya/variants/meliks/Makefile.mk
View file

@ -5,3 +5,4 @@ romstage-y += memory.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
ramstage-y += gpio.c
ramstage-y += ramstage.c

56
src/mainboard/google/brya/variants/meliks/ramstage.c Normal file
View file

@ -0,0 +1,56 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#define __SIMPLE_DEVICE__
#include <soc/ramstage.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/mmio.h>
#define DPHY_0_CLOCK_LANE_TIMING 0x162180
#define RESET_DPHY_0_CLOCK_LANE_TIMING 0
static uint32_t igd_mem_base(void)
{
uint32_t igd_bar = pci_read_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0);
/* Check if the controller is disabled or not present */
if (igd_bar == 0 || igd_bar == 0xffffffff)
return 0;
return (igd_bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
}
static void igd_set_mem_base(uint32_t base)
{
uint16_t igd_cmd;
pci_write_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, base);
igd_cmd = pci_read_config16(SA_DEVFN_IGD, PCI_COMMAND);
pci_write_config16(SA_DEVFN_IGD, PCI_COMMAND, igd_cmd | PCI_COMMAND_MEMORY);
}
static void reset_display_dphy_clock(void)
{
uint32_t igd_base = igd_mem_base();
bool need_temp_bar = false;
if (!igd_base) {
need_temp_bar = true;
igd_base = CONFIG_GFX_GMA_DEFAULT_MMIO;
igd_set_mem_base(igd_base);
}
write32p(igd_base + DPHY_0_CLOCK_LANE_TIMING, RESET_DPHY_0_CLOCK_LANE_TIMING);
if (need_temp_bar)
igd_set_mem_base(0);
}
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
/* DPHY CLK timing is not reset if the boot reason is warm boot. Hence to make
the function consistent relies on software forcing the DPHY CLK timing to
the HW default */
reset_display_dphy_clock();
}