From 725ab7b06604639d4e4dfbc4e833353914bf00de Mon Sep 17 00:00:00 2001 From: Ingo Reitz <9l@9lo.re> Date: Fri, 29 Aug 2025 05:35:06 +0200 Subject: [PATCH] soc/mediatek/common: Increase WAIT_AUX_READY_TIME_MS Increase WAIT_AUX_READY_TIME_MS from 1 ms to 3 ms fix a 20s timeout bug on Google/Cherry/Tomato and possibly other MediaTek Chromebooks introduced in commit 6ba2df9be5 (soc/mediatek/common: Use polling to reduce eDP HPD wait time). Change-Id: I6f41c3733e67c85e4aea3ce3b641a98cad94715c Signed-off-by: Ingo Reitz <9l@9lo.re> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88991 Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Paul Menzel --- src/soc/mediatek/common/dp/include/soc/dptx_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h index 8a42a63996..fb3c1daf57 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h @@ -70,7 +70,7 @@ #define MAX_LANECOUNT 4 #define HPD_WAIT_TIMEOUT_MS 200 -#define WAIT_AUX_READY_TIME_MS 1 +#define WAIT_AUX_READY_TIME_MS 3 enum { DP_LANECOUNT_1 = 0x1,