From 7256aba07e9567ef8d73f05e1f80c4d45fd57bda Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Tue, 29 Oct 2013 13:36:10 -0700 Subject: [PATCH] tegra124: small cleanups of the code Before I start moving things around I'm just cleaning house. I'm so used to graphics exploding that I like to take it easy. BUG=None TEST=builds and boots to linux, with a dev screen on the way BRANCH=None Change-Id: I195520aa02ea82adf9e1d2befddc0528f5d15978 Signed-off-by: Ronald G. Minnich Reviewed-on: https://chromium-review.googlesource.com/174995 Commit-Queue: Ronald Minnich Tested-by: Ronald Minnich Reviewed-by: Gabe Black --- src/soc/nvidia/tegra/dp.c | 152 ++--------------------- src/soc/nvidia/tegra124/displayhack.c | 167 +++++--------------------- 2 files changed, 35 insertions(+), 284 deletions(-) diff --git a/src/soc/nvidia/tegra/dp.c b/src/soc/nvidia/tegra/dp.c index 537c56ccf7..4a3f3277d6 100644 --- a/src/soc/nvidia/tegra/dp.c +++ b/src/soc/nvidia/tegra/dp.c @@ -29,7 +29,7 @@ // this is really broken. #include #include -#undef DEBUG + extern int dump; unsigned long READL(void* p); void WRITEL(unsigned long value, void* p); @@ -38,11 +38,6 @@ static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) { void *addr = dp->aux_base + (u32)(reg <<2); u32 reg_val = READL(addr); -#ifdef DEBUG - - printk(BIOS_SPEW, "JZ: %s: reg: %p, val: %#x\n", __func__, - addr, reg_val); -#endif return reg_val; } @@ -50,10 +45,6 @@ static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, u32 reg, u32 val) { void *addr = dp->aux_base + (u32)(reg <<2); -#ifdef DEBUG - printk(BIOS_SPEW, "JZ: %s: reg: %p, val: %#x\n", __func__, - addr, val); -#endif WRITEL(val, addr); } @@ -154,9 +145,7 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, printk(BIOS_SPEW,"dp: aux write transaction timeout\n"); *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - // printk(BIOS_SPEW, "dp: %s: aux stat: 0x%08x\n", __func__, *aux_stat); - /* Ignore I2C errors on fpga */ if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || @@ -256,12 +245,12 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, return -1; } -if (0){ - *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { - printk(BIOS_SPEW,"dp: HPD is not detected\n"); - //return EFAULT; - } + if (0){ + *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); + if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { + printk(BIOS_SPEW,"dp: HPD is not detected\n"); + //return EFAULT; + } } tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); @@ -397,45 +386,6 @@ static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, return ret; } -#if 0 -static void tegra_dc_dpaux_enable(struct tegra_dc_dp_data *dp) -{ - /* clear interrupt */ - tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff); - /* do not enable interrupt for now. Enable them when Isr in place */ - tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0); - - tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL, - DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 | - DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 | - 0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT | - DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE); -} - -static int tegra_dc_dp_lower_config(struct tegra_dc_dp_data *dp, - struct tegra_dc_dp_link_config *cfg) -{ - if (cfg->link_bw == SOR_LINK_SPEED_G1_62) { - if (cfg->max_link_bw > SOR_LINK_SPEED_G1_62) - cfg->link_bw = SOR_LINK_SPEED_G2_7; - cfg->lane_count /= 2; - } else if (cfg->link_bw == SOR_LINK_SPEED_G2_7) - cfg->link_bw = SOR_LINK_SPEED_G1_62; - else if (cfg->link_bw == SOR_LINK_SPEED_G5_4) { - if (cfg->lane_count == 1) { - cfg->link_bw = SOR_LINK_SPEED_G2_7; - cfg->lane_count = cfg->max_lane_count; - } else - cfg->lane_count /= 2; - } else { - printk(BIOS_ERR, - "dp: Error link rate %d\n", cfg->link_bw); - return 0; - } - return (cfg->lane_count > 0); -} - -#endif static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp, struct tegra_dc_dp_link_config *cfg) { @@ -495,84 +445,10 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp, cfg->lane_count = cfg->max_lane_count; cfg->link_bw = cfg->max_link_bw; cfg->enhanced_framing = cfg->support_enhanced_framing; - -#if 0 // jz - tegra_dc_dp_calc_config(dp, dp->mode, cfg); return 0; -#else -// return -1; // do link_training - return 0; // do link_training -#endif // jz } -#if 0 -static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp, - struct tegra_dc_dp_link_config *cfg, struct tegra_dc_mode *mode) -{ - struct tegra_dc_dp_link_config temp_cfg; -#if 0 - /* kernel thing. */ - if (!mode->pclk || !mode->h_active || !mode->v_active) { - dev_err(&dp->dc->ndev->dev, - "dp: error mode configuration"); - return -EINVAL; - } -#endif - if (!cfg->max_link_bw || !cfg->max_lane_count) { - printk(BIOS_SPEW, - "dp: error link configuration"); - return -1; - } - - cfg->is_valid = 0; - memcpy(&temp_cfg, cfg, sizeof(temp_cfg)); - - temp_cfg.link_bw = temp_cfg.max_link_bw; - temp_cfg.lane_count = temp_cfg.max_lane_count; - - while (tegra_dc_dp_calc_config(dp, mode, &temp_cfg) && - tegra_dp_link_config(dp, &temp_cfg)) { - /* current link cfg is doable */ - memcpy(cfg, &temp_cfg, sizeof(temp_cfg)); - - /* try to lower the config */ - if (!tegra_dc_dp_lower_config(dp, &temp_cfg)) - break; - } - - return cfg->is_valid ? 0 : -1; -} -#endif -#if 0 -static long tegra_dc_dp_setup_clk(struct tegra_dc *dc, struct clk *clk) -{ - struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc); - struct clk *sor_clk = dp->sor->sor_clk; - struct clk *parent_clk; - - if (clk == dc->clk) { - parent_clk = clk_get_sys(NULL, - dc->out->parent_clk ? : "pll_d_out0"); - if (clk_get_parent(clk) != parent_clk) - clk_set_parent(clk, parent_clk); - } - - tegra_dc_sor_setup_clk(dp->sor, clk, false); - - parent_clk = clk_get(NULL, "pll_dp"); - - if (clk_get_parent(sor_clk) != parent_clk) - clk_set_parent(sor_clk, parent_clk); - clk_set_rate(parent_clk, 270000000); - - if (!tegra_is_clk_enabled(parent_clk)) - clk_prepare_enable(parent_clk); - - return tegra_dc_pclk_round_rate(dc, dp->sor->dc->mode.pclk); -} - -#endif //struct tegra_dc dc_data = {0}; struct tegra_dc_sor_data sor_data = {0}; struct tegra_dc_dp_data dp_data = {0}; @@ -624,10 +500,6 @@ void dp_bringup(u32 winb_addr) if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg)) printk(BIOS_SPEW,"dp: failed to init link configuration\n"); -#if 0 - if (tegra_dc_dp_link_training(dp, &dp->link_cfg)) - printk(BIOS_SPEW,"dp: failed to do lt\n"); -#endif dp_link_training((u32)(dp->link_cfg.lane_count), (u32)(dp->link_cfg.link_bw)); @@ -647,18 +519,8 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, (u32)dp->link_cfg.alt_scramber_reset_cap, pclk_freq, dp->link_cfg.link_bw * 27); - void dp_test(void); - //dp_test(); -#if 0 // jz, next - else if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, - dp->mode)) - printk(BIOS_SPEW,"dp irq: cannot get working config\n"); - -// if (tegra_dp_link_config(dp, &dp->link_cfg)) -// printk(BIOS_SPEW,"dp: failed to set link configuration\n"); -#endif // rgm } void debug_dpaux_print(u32 addr, u32 size) diff --git a/src/soc/nvidia/tegra124/displayhack.c b/src/soc/nvidia/tegra124/displayhack.c index cd6d3dd179..847d6f6057 100644 --- a/src/soc/nvidia/tegra124/displayhack.c +++ b/src/soc/nvidia/tegra124/displayhack.c @@ -382,13 +382,6 @@ void init_sor_regs(void) WRITEL(0x0, (void *)(0x60006000 + 0x414)); // CLK_SOURCE_SOR0 = PLLP //WRITEL(0xc000c000, (0x60006000 + 0x414)); // CLK_SOURCE_SOR0 = CLK_M -#if 0 - u32 reg_val; - reg_val = READL((void *)(0x60006000 + 0x414)); - reg_val &= ~(0x7 << 29); - reg_val |= (0x4 << 29); // PLLC - WRITEL(reg_val, (void *)(0x60006000 + 0x414)); // CLK_SOURCE_SOR0 = PLLC -#endif #if 1 #define SOR_WRITE(reg, val) \ @@ -752,6 +745,22 @@ static int dpaux_check(u32 bytes, u32 data, u32 mask) return -1; } +/* Modify the drive parameters for DP. There are up to four DP + * lanes. In principle, each lane can have different current, + * pre-emphasis, and postcur values. Nobody individualizes them; every + * single driver I've seen drives all the lanes to the same value + * (across x86 and ARM code). Actualy adjusting them individually and + * getting it all to work is probably a PhD thesis anyway. So, rather + * than the very complex code we see many places, the people who wrote + * this code realize: we can represent the 'volume' as a number in the + * range 0..3, with '0' as the base and '3' as being 'not to exceed'. + * + * So they abstract the values away, take care of the proper values, + * and set it all in one blow. Very nice. By far the easiest one of + * these functions we've seen. Sure, they could have constants, but + * nobody knows what PRE_EMPHASIS_3_5 and the other values actually + * *mean* anyway. Well, the hardware guys might. + */ static void pattern_level(u32 current, u32 preemph, u32 postcur) { printk(BIOS_SPEW, "set level:%d %d %d\n", current, preemph, postcur); @@ -785,7 +794,9 @@ static void pattern_level(u32 current, u32 preemph, u32 postcur) static int dp_training(u32 level, u32 check, u32 speed) { - + /* The levels are one of four choices. This code + * packs them into the three lowest nibl's. We may change this. + */ u32 dc_lv = level & 0x0f; u32 pe_lv = (level >> 4) & 0x0f; u32 pc_lv = (level >> 8) & 0x0f; @@ -880,11 +891,7 @@ void dp_link_training(u32 lanes, u32 speed) //REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0,SOR0_CLK_SEL0, 1) //sor clk=pad macro output reg_val = readl((void *)(0x60006000 + 0x414)); reg_val |= SOR0_CLK_SEL0; -#if 0 // pllp_debug - reg_val &= ~(0x7 << 29); - reg_val |= (0x6 << 29); - reg_val |= (SOR0_CLK_SEL0 | SOR0_CLK_SEL1); -#endif + writel(reg_val, (void *)(0x60006000 + 0x414)); SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL0_0, @@ -971,18 +978,7 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) // 720x480: 27.00 , 594/22, dp CEA // 640x480: 23.75 , 475/20, dp VESA -#if 0 - //LG 12.85", 285.25MHz, neg hsync/vsync - // 2560 x 1700 - //hfrontporch=48, hsyncwidth=32, hbackporch=80 - //vfrontporch=3, vsyncwidth=10, vbackporch=36 - %PLL_FREQ = 570 - % PLL_DIV = 2 - % SYNC_WIDTH = (10 << 16) | 32 - % BACK_PORCH = (36 << 16) | 80 - % FRONT_PORCH = (3 << 16) | 48 % HSYNC_NEG = 1 % VSYNC_NEG = 1 -#endif - u32 PLL_FREQ = 570; + u32 PLL_FREQ = 570; u32 PLL_DIV = 2; u32 SYNC_WIDTH = (10 << 16) | 32; u32 BACK_PORCH = (36 << 16) | 80; @@ -1009,7 +1005,7 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) __func__, panel_id, width, height); return pclk_freq; } -#if 1 // jz + // clock(plld2, %PLL_FREQ) // PLL_FREQ = 570 writel(0, (void *)(0x60006000 + 0x4bc)); // plld2_misc writel(0x13400000, (void *)(0x60006000 + 0x570)); // plld2_ss_cfg @@ -1030,7 +1026,7 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) reg_val |= PLLD2_OUT0; writel(reg_val, (void *)(0x60006000 + 0x138)); udelay(10); -#endif + PLL_FREQ = PLL_FREQ * 1000000; pclk_freq = PLL_FREQ / PLL_DIV; PLL_FREQ_I = PLL_FREQ / 1000000; @@ -1039,7 +1035,7 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) PCLK_FREQ_F = div_f(PLL_FREQ, PLL_DIV * 1000000, 100); FRATE_I = PLL_FREQ / (PLL_DIV * TOTAL_PIXELS); FRATE_F = div_f(PLL_FREQ, (PLL_DIV * TOTAL_PIXELS), 100); - //bug 1021453 + //bug 1021453 BACK_PORCH = BACK_PORCH - 0x10000; FRONT_PORCH = FRONT_PORCH + 0x10000; @@ -1105,61 +1101,7 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD, (SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 << SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT)); -#if 0 // ts - - %SHIFT_CLK_DIVIDER = %PLL_DIV * 2 - 2 - % DISP_ACTIVE = (%HEIGHT << 16) | %WIDTH - % DISP_TOTAL = %DISP_ACTIVE + %SYNC_WIDTH + %BACK_PORCH + %FRONT_PORCH - % SYNC_END = %SYNC_WIDTH - 0x10001 - % BLANK_END = %SYNC_END + %BACK_PORCH - % BLANK_START = %BLANK_END + %DISP_ACTIVE - % TOTAL_PIXELS = (%DISP_TOTAL & 0xffff) * (%DISP_TOTAL >> 16) - - % pclk_freq = %PLL_FREQ / %PLL_DIV - % PLL_FREQ_I = %PLL_FREQ / 1000000 - % PLL_FREQ_F = div_f(%PLL_FREQ, 1000000, 100) - % PCLK_FREQ_I = %PLL_FREQ / (%PLL_DIV * 1000000) - % PCLK_FREQ_F = div_f(%PLL_FREQ, %PLL_DIV * 1000000, 100) - % FRATE_I = %PLL_FREQ / (%PLL_DIV * %TOTAL_PIXELS) - % FRATE_F = div_f(%PLL_FREQ, (%PLL_DIV * %TOTAL_PIXELS), 100) - //bug 1021453 - % BACK_PORCH = %BACK_PORCH - 0x10000 - % FRONT_PORCH = %FRONT_PORCH + 0x10000 - printk(BIOS_SPEW, "ACTIVE: %dx%d\n", (%DISP_ACTIVE & 0xFFFF), - (%DISP_ACTIVE >> 16)) - printk(BIOS_SPEW, "TOTAL: %dx%d\n", (%DISP_TOTAL & 0xffff), - (%DISP_TOTAL >> 16)) - printk(BIOS_SPEW, "PLL Freq: %d.%d MHz\n", %PLL_FREQ_I, - %PLL_FREQ_F) - printk(BIOS_SPEW, "Pclk Freq: %d.%d MHz\n", %PCLK_FREQ_I, - %PCLK_FREQ_F) - printk(BIOS_SPEW, "Frame Rate: %d.%d Hz\n", %FRATE_I, %FRATE_F) - printk(BIOS_SPEW, "\n") - - REG(DC_CMD_STATE_ACCESS_0, 0x00000004) - REG(DC_DISP_DISP_CLOCK_CONTROL_0, %SHIFT_CLK_DIVIDER) - //Raster Timing - REG(DC_DISP_DISP_TIMING_OPTIONS_0, 0x00000001) - REG(DC_DISP_REF_TO_SYNC_0, 0x00010001) - REG(DC_DISP_SYNC_WIDTH_0, %SYNC_WIDTH) - REG(DC_DISP_BACK_PORCH_0, %BACK_PORCH) - REG(DC_DISP_DISP_ACTIVE_0, %DISP_ACTIVE) - REG(DC_DISP_FRONT_PORCH_0, %FRONT_PORCH) - - REG(DC_DISP_DISP_WIN_OPTIONS_0, SOR_ENABLE, 1) - REG(SOR_NV_PDISP_HEAD_STATE1_0, %DISP_TOTAL) - REG(SOR_NV_PDISP_HEAD_STATE2_0, %SYNC_END) - REG(SOR_NV_PDISP_HEAD_STATE3_0, %BLANK_END) - REG(SOR_NV_PDISP_HEAD_STATE4_0, %BLANK_START) - REG(SOR_NV_PDISP_SOR_STATE1_0, ASY_HSYNCPOL, %HSYNC_NEG) - REG(SOR_NV_PDISP_SOR_STATE1_0, ASY_VSYNCPOL, %VSYNC_NEG) - REG(SOR_NV_PDISP_SOR_STATE1_0, ASY_PROTOCOL, DP_A) - REG(SOR_NV_PDISP_SOR_STATE1_0, ASY_CRCMODE, COMPLETE_RASTER) - REG(SOR_NV_PDISP_SOR_STATE1_0, ASY_SUBOWNER, NONE) - REG(SOR_NV_PDISP_SOR_STATE1_0, ASY_OWNER, HEAD0) - return (%pclk_freq) -#endif - printk(BIOS_SPEW, "%s: exit\n", __func__); + printk(BIOS_SPEW, "%s: exit\n", __func__); return pclk_freq; } @@ -1302,14 +1244,6 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, (SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_444 << SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT)); } -#if 0 -#define DC_B_WIN_BD_SIZE_0 0xd84 -#define DC_B_WIN_BD_PRESCALED_SIZE_0 0xd86 -#define DC_B_WIN_BD_LINE_STRIDE_0 0xd8a -#define DC_B_WIN_BD_COLOR_DEPTH_0 0xd83 -#define DC_B_WINBUF_BD_START_ADDR_0 0xdc0 -#define DC_B_WIN_BD_DDA_INCREMENT_0 0xd89 -#endif #define SRC_BPP 16 #define COLORDEPTH 0x6 @@ -1341,9 +1275,7 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, DCA_WRITE(DC_CMD_DISPLAY_COMMAND_0, 0x00000020); SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0, 0x00000e48); - //AuxPrint(0x200, 16) - // %d = (%enhanced_framing << 7) | %lanes dpaux_write(0x101, 1, (enhanced_framing << 7) | lane_count); if (panel_edp) dpaux_write(0x10A, 1, 1); @@ -1364,7 +1296,7 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, SOR_WRITE(SOR_NV_PDISP_SOR_PWR_0, 0x80000001); printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_PWR_0.DONE\n"); dp_poll_register((void *)0x54540054, 0x00000000, 0x80000000, 1000); - //SOR_NV_PDISP_SOR_PWR_0 + //SOR_NV_PDISP_SOR_PWR_0 //sor_update SOR_WRITE(SOR_NV_PDISP_SOR_STATE0_0, 0x00000000); SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE1_0, 0x00000006); @@ -1389,56 +1321,13 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, DCA_WRITE(DC_CMD_STATE_ACCESS_0, 4); DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x0000ffff); /* enable win_b */ -#if 1 + DCA_READ_M_WRITE(DC_B_WIN_BD_WIN_OPTIONS_0, DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD, (DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE << DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT)); -#endif + printk(BIOS_SPEW, "JZ: %s: f_ret @ line %d\n", __func__, __LINE__); } -static inline void dc_act(void) -{ - DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x0000ffff); -} - -void dp_test(void); -void dp_test(void) -{ - u32 color = BLACK; - u32 final = GREY; - u32 i; - - printk(BIOS_SPEW, "%s: entry\n", __func__); - - for (i = 0; i < 10; ++i) { - printk(BIOS_SPEW, "TEST %d\n", i); - switch (i % 3) { - case 0: - color = RED; - case 1: - color = GREEN; - case 2: - color = BLUE; - } - - DCA_WRITE(DC_DISP_BLEND_BACKGROUND_COLOR_0, color); - dc_act(); - delay(5); - } - - DCA_WRITE(DC_DISP_BLEND_BACKGROUND_COLOR_0, final); - dc_act(); - udelay(1500); - -// DCA_WRITE (DC_DISP_BLEND_BACKGROUND_COLOR_0, BLACK); -// dc_act(); -// udelay(1500); - - DCA_WRITE(DC_CMD_STATE_ACCESS_0, 4); - dc_act(); - - printk(BIOS_SPEW, "%s: exit\n", __func__); -}