From 72401fc03924866e63264a228125aaa1f09cccaa Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Tue, 4 Feb 2025 15:56:22 +0100 Subject: [PATCH] soc/amd/mendocino/chipset_*: Enable gpp_bridge_[a/b/c] by default Since FSP doesn't support disabling bridges and has no UPDs for that, they must be enabled in DT to make sure they are properly initialized during PCI enumeration as expected by the payload (EDK2 for example). It might be OK to have them set to off when all devices behind the bridge are also off and FSP disables those secondary devices. In general something that cannot be hidden/shut off shouldn't be marked as such, as later stages (payload/OS) might find it active, but unconfigured. Change-Id: Ife30f73495d44c98717e147602de10f5a6a89358 Signed-off-by: Maximilian Brune Reviewed-on: https://review.coreboot.org/c/coreboot/+/86273 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/mendocino/chipset_mendocino.cb | 4 ++-- src/soc/amd/mendocino/chipset_rembrandt.cb | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 6ee1e63f18..3458caed06 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -16,7 +16,7 @@ chip soc/amd/mendocino device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy device function, do not disable - device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + device pci 08.1 alias gpp_bridge_a on # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) @@ -65,7 +65,7 @@ chip soc/amd/mendocino device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID # When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index ef3bfa9a56..aef0a8978b 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -18,7 +18,7 @@ chip soc/amd/mendocino device pci 02.6 alias gpp_bridge_5 hidden ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy device function, do not disable - device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + device pci 08.1 alias gpp_bridge_a on # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) @@ -67,8 +67,8 @@ chip soc/amd/mendocino device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B - device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + device pci 08.2 alias gpp_bridge_b on ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B + device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID # When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops