diff --git a/configs/config.qotom_qdnv01 b/configs/config.qotom_qdnv01 new file mode 100644 index 0000000000..1042ec6de4 --- /dev/null +++ b/configs/config.qotom_qdnv01 @@ -0,0 +1,5 @@ +CONFIG_VENDOR_QOTOM=y +CONFIG_MAINBOARD_PART_NUMBER="Qotom QDNV01" +CONFIG_ENABLE_HSUART=y +CONFIG_USE_DENVERTON_NS_FSP_CAR=y +# CONFIG_SMMSTORE is not set diff --git a/src/mainboard/qotom/Kconfig b/src/mainboard/qotom/Kconfig new file mode 100644 index 0000000000..066df4af96 --- /dev/null +++ b/src/mainboard/qotom/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_QOTOM + +choice + prompt "Mainboard model" + +source "src/mainboard/qotom/*/Kconfig.name" + +endchoice + +source "src/mainboard/qotom/*/Kconfig" + +config MAINBOARD_VENDOR + default "Qotom" + +endif # VENDOR_QOTOM diff --git a/src/mainboard/qotom/Kconfig.name b/src/mainboard/qotom/Kconfig.name new file mode 100644 index 0000000000..c20833d139 --- /dev/null +++ b/src/mainboard/qotom/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_QOTOM + bool "Qotom" diff --git a/src/mainboard/qotom/qdnv01/Kconfig b/src/mainboard/qotom/qdnv01/Kconfig new file mode 100644 index 0000000000..269cee07d1 --- /dev/null +++ b/src/mainboard/qotom/qdnv01/Kconfig @@ -0,0 +1,23 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_QOTOM_QDNV01 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_DENVERTON_NS + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + select DRIVERS_ASPEED_AST2050 + select MAINBOARD_USES_IFD_10GBE_0_REGION + select MAINBOARD_USES_IFD_10GBE_1_REGION + +config MAINBOARD_DIR + default "qotom/qdnv01" + +config MAINBOARD_PART_NUMBER + default "QDNV01" + +config CBFS_SIZE + default 0x800000 + +endif # BOARD_QOTOM_QDNV01 diff --git a/src/mainboard/qotom/qdnv01/Kconfig.name b/src/mainboard/qotom/qdnv01/Kconfig.name new file mode 100644 index 0000000000..a3a2270c3b --- /dev/null +++ b/src/mainboard/qotom/qdnv01/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_QOTOM_QDNV01 + bool "QDNV01" diff --git a/src/mainboard/qotom/qdnv01/Makefile.mk b/src/mainboard/qotom/qdnv01/Makefile.mk new file mode 100644 index 0000000000..8917ff6f64 --- /dev/null +++ b/src/mainboard/qotom/qdnv01/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += hsio.c + +ramstage-y += ramstage.c +ramstage-y += hsio.c + +CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ diff --git a/src/mainboard/qotom/qdnv01/acpi/mainboard.asl b/src/mainboard/qotom/qdnv01/acpi/mainboard.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/qotom/qdnv01/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/qotom/qdnv01/acpi/mainboard_pci_irqs.asl b/src/mainboard/qotom/qdnv01/acpi/mainboard_pci_irqs.asl new file mode 100644 index 0000000000..3482e23761 --- /dev/null +++ b/src/mainboard/qotom/qdnv01/acpi/mainboard_pci_irqs.asl @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This is board specific information: IRQ routing */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // [GREG]: Global Registers + Package() { 0x0004ffff, 0, 0, 16 }, + + // [RCEC]: Root Complex Event Collector + Package() { 0x0005ffff, 0, 0, 23 }, + + // [VRP2]: Virtual root port 2 + Package() { 0x0006ffff, 2, 0, 18 }, + + // [PEX0]: PCI Express Port 0 + Package() { 0x0009ffff, 0, 0, 16 }, + + // [PEX1]: PCI Express Port 1 + Package() { 0x000affff, 1, 0, 17 }, + + // [PEX2]: PCI Express Port 2 + Package() { 0x000bffff, 2, 0, 18 }, + + // [PEX3]: PCI Express Port 3 + Package() { 0x000cffff, 3, 0, 19 }, + + // [PEX4]: PCI Express Port 4 + Package() { 0x000effff, 0, 0, 20 }, + + // [PEX5]: PCI Express Port 5 + Package() { 0x000fffff, 1, 0, 21 }, + + // [PEX6]: PCI Express Port 6 + Package() { 0x0010ffff, 2, 0, 22 }, + + // [PEX7]: PCI Express Port 7 + Package() { 0x0011ffff, 3, 0, 23 }, + + // [SMB1]: SMBus controller + Package() { 0x0012ffff, 0, 0, 16 }, + + // [SAT0]: SATA controller 0 + Package() { 0x0013ffff, 0, 0, 20 }, + + // [SAT1]: SATA controller 1 + Package() { 0x0014ffff, 0, 0, 21 }, + + // [XHC0]: XHCI USB controller + Package() { 0x0015ffff, 0, 0, 19 }, + + // [VRP0]: Virtual root port 0 + Package() { 0x0016ffff, 0, 0, 16 }, + + // [VRP1]: Virtual root port 1 + Package() { 0x0017ffff, 1, 0, 17 }, + + // [HECI]: ME HECI + Package() { 0x0018ffff, 0, 0, 16 }, + + // [HEC2]: ME HECI2 + Package() { 0x0018ffff, 1, 0, 17 }, + + // [MEKT]: MEKT on PCH + Package() { 0x0018ffff, 2, 0, 18 }, + + // [HEC3]: ME HECI3 + Package() { 0x0018ffff, 3, 0, 19 }, + + // [UAR0]: UART 0 + Package() { 0x001affff, 0, 0, 16 }, + + // [UAR1]: UART 1 + Package() { 0x001affff, 1, 0, 17 }, + + // [UAR2]: UART 2 + Package() { 0x001affff, 2, 0, 18 }, + + // [EMMC]: eMMC + Package() { 0x001cffff, 0, 0, 16 }, + + // [P2SB]: Primary to sideband bridge + // [SMB0]: SMBus controller + // [NPK0]: Northpeak DFX + Package() { 0x001fffff, 0, 0, 23 }, + }) + } Else { + Return (Package() { + // [GREG]: Global Registers 0:4.0 + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + + // [RCEC]: Root Complex Event Collector 0:5.0 + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + + // [VRP2]: Virtual root port 2 0:6.0 + Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + + // [PEX0]: PCI Express Port 0 0:9.0 + Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + + // [PEX1]: PCI Express Port 1 0:a.0 + Package() { 0x000affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + + // [PEX2]: PCI Express Port 2 0:b.0 + Package() { 0x000bffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + + // [PEX3]: PCI Express Port 3 0:c.0 + Package() { 0x000cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + + // [PEX4]: PCI Express Port 4 0:e.0 + Package() { 0x000effff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + + // [PEX5]: PCI Express Port 5 0:f.0 + Package() { 0x000fffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + + // [PEX6]: PCI Express Port 6 0:10.0 + Package() { 0x0010ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, + + // [PEX7]: PCI Express Port 7 0:11.0 + Package() { 0x0011ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, + + // [SMB1]: SMBus controller 0:12.0 + Package() { 0x0012ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + + // [SAT0]: SATA controller 0 0:13.0 + Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + + // [SAT1]: SATA controller 1 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + + // [XHC0]: XHCI USB controller 0:15.0 + Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + + // [VRP0]: Virtual root port 0 0:16.0 + Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + + // [VRP1]: Virtual root port 1 0:17.0 + Package() { 0x0017ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + + // [HECI]: ME HECI 0:18.0 + Package() { 0x0018ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + + // [HEC2]: ME HECI2 0:18.1 + Package() { 0x0018ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + + // [MEKT]: MEKT on PCH 0:18.2 + Package() { 0x0018ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + + // [HEC3]: ME HECI3 0:18.3 + Package() { 0x0018ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + + // [UAR0]: UART 0 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + + // [UAR1]: UART 1 0:1a.1 + Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + + // [UAR2]: UART 2 0:1a.2 + Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + + // [EMMC]: eMMC 0:1c.0 + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + + // [P2SB]: Primary to sideband bridge + // [SMB0]: SMBus controller + // [NPK0]: Northpeak DFX + Package() { 0x001ffffF, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } +} diff --git a/src/mainboard/qotom/qdnv01/acpi/platform.asl b/src/mainboard/qotom/qdnv01/acpi/platform.asl new file mode 100644 index 0000000000..bbee0a2787 --- /dev/null +++ b/src/mainboard/qotom/qdnv01/acpi/platform.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/qotom/qdnv01/acpi_tables.c b/src/mainboard/qotom/qdnv01/acpi_tables.c new file mode 100644 index 0000000000..b6e3846f28 --- /dev/null +++ b/src/mainboard/qotom/qdnv01/acpi_tables.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; +} diff --git a/src/mainboard/qotom/qdnv01/board_info.txt b/src/mainboard/qotom/qdnv01/board_info.txt new file mode 100644 index 0000000000..88971b9bfd --- /dev/null +++ b/src/mainboard/qotom/qdnv01/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Qotom +Board name: QDNV01 +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/qotom/qdnv01/bootblock.c b/src/mainboard/qotom/qdnv01/bootblock.c new file mode 100644 index 0000000000..3b3fd22940 --- /dev/null +++ b/src/mainboard/qotom/qdnv01/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + + +void bootblock_mainboard_early_init(void) +{ +} diff --git a/src/mainboard/qotom/qdnv01/devicetree.cb b/src/mainboard/qotom/qdnv01/devicetree.cb new file mode 100644 index 0000000000..b7ba01f1ac --- /dev/null +++ b/src/mainboard/qotom/qdnv01/devicetree.cb @@ -0,0 +1,78 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/denverton_ns + + # configure pirq routing + register "pirqa_routing" = "11" + register "pirqb_routing" = "10" + register "pirqc_routing" = "06" + register "pirqd_routing" = "07" + register "pirqe_routing" = "12" + register "pirqf_routing" = "14" + register "pirqg_routing" = "15" + register "pirqh_routing" = "15" + # configure device interrupt routing + register "ir00_routing" = "0x3217" # IR00, Dev31 + register "ir01_routing" = "0x3210" # IR01, Dev22 + register "ir02_routing" = "0x3211" # IR02, Dev23 + register "ir03_routing" = "0x3217" # IR03, Dev5 + register "ir04_routing" = "0x3212" # IR04, Dev6 + register "ir05_routing" = "0x3210" # IR05, Dev24 + register "ir06_routing" = "0x3214" # IR06, Dev19 + register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12 + register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17 + register "ir09_routing" = "0x3213" # IR09, Dev21 + register "ir10_routing" = "0x3210" # IR10, Dev26/18 + register "ir11_routing" = "0x3215" # IR11, Dev20 + register "ir12_routing" = "0x3210" # IR12, Dev27 + # configure interrupt polarity control + register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow + register "ipc1" = "0x00000000" # IPC1 + register "ipc2" = "0x00000000" # IPC2 + register "ipc3" = "0x00000000" # IPC3 + + device cpu_cluster 0 on end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 04.0 on end # RAS + device pci 05.0 on end # RCEC (Root Complex Event Collector) + device pci 06.0 on end # Virtual root port 2 (QAT) + device pci 09.0 on end # PCI Express Port 0 + device pci 0a.0 on end # PCI Express Port 1 + device pci 0b.0 on # PCI Express Port 2 + device pci 00.0 on end # Intel Ethernet Controller I226-V + end + device pci 0c.0 on # PCI Express Port 3 + device pci 00.0 on end # Intel Ethernet Controller I226-V + end + device pci 0e.0 on # PCI Express Port 4 + device pci 00.0 on end # Intel Ethernet Controller I226-V + end + device pci 0f.0 on # PCI Express Port 5 + device pci 00.0 on end # Intel Ethernet Controller I226-V + end + device pci 10.0 on # PCI Express Port 6 + device pci 00.0 on end # Intel Ethernet Controller I226-V + end + device pci 11.0 on # PCI Express Port 7 + device pci 00.0 on # ASPEED PCI-to-PCI bridge 1a03:1150 + device pci 00.0 on end # ASPEED VGA controller 1a03:2000 + end + end + device pci 12.0 on end # SMBus Controller + device pci 13.0 on end # SATA Controller 0 + device pci 14.0 on end # SATA Controller 1 + device pci 15.0 on end # XHCI USB Controller + device pci 16.0 on end # Virtual root port 0 (10GBE0) + device pci 17.0 on end # Virtual root port 1 (10GBE1) + device pci 18.0 on end # CSME HECI 1 + device pci 1a.0 on end # UART 0 + device pci 1a.1 on end # UART 1 + device pci 1a.2 on end # UART 2 + device pci 1f.0 on end # LPC or eSPI + device pci 1f.2 on end # PMC/ACPI + device pci 1f.4 on end # SMBus Controller + device pci 1f.5 on end # SPI Controller + end +end diff --git a/src/mainboard/qotom/qdnv01/dsdt.asl b/src/mainboard/qotom/qdnv01/dsdt.asl new file mode 100644 index 0000000000..3fa7422c46 --- /dev/null +++ b/src/mainboard/qotom/qdnv01/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include + + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + #include +} diff --git a/src/mainboard/qotom/qdnv01/gpio.h b/src/mainboard/qotom/qdnv01/gpio.h new file mode 100644 index 0000000000..b065369929 --- /dev/null +++ b/src/mainboard/qotom/qdnv01/gpio.h @@ -0,0 +1,622 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_GPIO_H +#define _MAINBOARD_GPIO_H + +#include + +#ifndef __ACPI__ +const struct dnv_pad_config qdnv01_gpio_table[] = { + // GBE0_SDP0 (GPIO_14) + {NORTH_ALL_GBE0_SDP0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE1_SDP0 (GPIO_15) + {NORTH_ALL_GBE1_SDP0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE2_I2C_CLK (GPIO_16) + {NORTH_ALL_GBE0_SDP1, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE2_I2C_DATA (GPIO_17) + {NORTH_ALL_GBE1_SDP1, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE2_SDP0 (GPIO_18) + {NORTH_ALL_GBE0_SDP2, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE3_SDP0 (GPIO_19) + {NORTH_ALL_GBE1_SDP2, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE3_I2C_CLK (GPIO_20) + {NORTH_ALL_GBE0_SDP3, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE3_I2C_DATA (GPIO_21) + {NORTH_ALL_GBE1_SDP3, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE2_LED0 (GPIO_22) + {NORTH_ALL_GBE2_LED0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE2_LED1 (GPIO_23) + {NORTH_ALL_GBE2_LED1, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE0_I2C_CLK (GPIO_24) + {NORTH_ALL_GBE0_I2C_CLK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE0_I2C_DATA (GPIO_25) + {NORTH_ALL_GBE0_I2C_DATA, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE1_I2C_CLK (GPIO_26) + {NORTH_ALL_GBE1_I2C_CLK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE1_I2C_DATA (GPIO_27) + {NORTH_ALL_GBE1_I2C_DATA, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // NCSI_RXD0 (GPIO_28) + {NORTH_ALL_NCSI_RXD0, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // NCSI_CLK_IN (GPIO_29) + {NORTH_ALL_NCSI_CLK_IN, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // NCSI_RXD1 (GPIO_30) + {NORTH_ALL_NCSI_RXD1, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // NCSI_CRS_DV (GPIO_31) + {NORTH_ALL_NCSI_CRS_DV, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // NCSI_ARB_IN (GPIO_32) + {NORTH_ALL_NCSI_ARB_IN, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // NCSI_TX_EN (GPIO_33) + {NORTH_ALL_NCSI_TX_EN, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // NCSI_TXD0 (GPIO_34) + {NORTH_ALL_NCSI_TXD0, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // NCSI_TXD1 (GPIO_35) + {NORTH_ALL_NCSI_TXD1, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // NCSI_ARB_OUT (GPIO_36) + {NORTH_ALL_NCSI_ARB_OUT, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // GBE0_LED0 (GPIO_37) + {NORTH_ALL_GBE0_LED0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // GBE0_LED1 (GPIO_38) + {NORTH_ALL_GBE0_LED1, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // GBE1_LED0 (GPIO_39) + {NORTH_ALL_GBE1_LED0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // GBE1_LED1 (GPIO_40) + {NORTH_ALL_GBE1_LED1, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // ADR-COMPLETE (GPIO_0) + {NORTH_ALL_GPIO_0, + {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PCIE_CLKREQ0_N (GPIO_41) + {NORTH_ALL_PCIE_CLKREQ0_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PCIE_CLKREQ1_N (GPIO_42) + {NORTH_ALL_PCIE_CLKREQ1_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PCIE_CLKREQ2_N (GPIO_43) + {NORTH_ALL_PCIE_CLKREQ2_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PCIE_CLKREQ3_N (GPIO_44) + {NORTH_ALL_PCIE_CLKREQ3_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // FORCE_POWER (GPIO_45) + {NORTH_ALL_PCIE_CLKREQ4_N, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE_MDC (GPIO_1) + {NORTH_ALL_GPIO_1, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE_MDIO (GPIO_2) + {NORTH_ALL_GPIO_2, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SVID_ALERT_N (GPIO_47) + {NORTH_ALL_SVID_ALERT_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SVID_DATA (GPIO_48) + {NORTH_ALL_SVID_DATA, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SVID_CLK (GPIO_49) + {NORTH_ALL_SVID_CLK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // THERMTRIP_N (GPIO_50) + {NORTH_ALL_THERMTRIP_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PROCHOT_N (GPIO_51) + {NORTH_ALL_PROCHOT_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // MEMHOT_N (GPIO_52) + {NORTH_ALL_MEMHOT_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT_CLK0 (GPIO_53) + {SOUTH_DFX_DFX_PORT_CLK0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT_CLK1 (GPIO_54) + {SOUTH_DFX_DFX_PORT_CLK1, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT0 (GPIO_55) + {SOUTH_DFX_DFX_PORT0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT1 (GPIO_56) + {SOUTH_DFX_DFX_PORT1, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT2 (GPIO_57) + {SOUTH_DFX_DFX_PORT2, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT3 (GPIO_58) + {SOUTH_DFX_DFX_PORT3, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT4 (GPIO_59) + {SOUTH_DFX_DFX_PORT4, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT5 (GPIO_60) + {SOUTH_DFX_DFX_PORT5, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT6 (GPIO_61) + {SOUTH_DFX_DFX_PORT6, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT7 (GPIO_62) + {SOUTH_DFX_DFX_PORT7, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT8 (GPIO_63) + {SOUTH_DFX_DFX_PORT8, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT9 (GPIO_134) + {SOUTH_DFX_DFX_PORT9, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT10 (GPIO_135) + {SOUTH_DFX_DFX_PORT10, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT11 (GPIO_136) + {SOUTH_DFX_DFX_PORT11, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT12 (GPIO_137) + {SOUTH_DFX_DFX_PORT12, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT13 (GPIO_138) + {SOUTH_DFX_DFX_PORT13, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT14 (GPIO_139) + {SOUTH_DFX_DFX_PORT14, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // DFX_PORT15 (GPIO_140) + {SOUTH_DFX_DFX_PORT15, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SPI_TPM_CS_N (GPIO_12) + {SOUTH_GROUP0_GPIO_12, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB5_GBE_ALRT_N (GPIO_13) + {SOUTH_GROUP0_SMB5_GBE_ALRT_N, + {GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // SMI (GPIO_98) + {SOUTH_GROUP0_PCIE_CLKREQ5_N, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntSmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // NMI (GPIO_99) + {SOUTH_GROUP0_PCIE_CLKREQ6_N, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntNmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE3_LED0 (GPIO_100) + {SOUTH_GROUP0_PCIE_CLKREQ7_N, + {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // UART0_RXD (GPIO_101) + {SOUTH_GROUP0_UART0_RXD, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // UART0_TXD (GPIO_102) + {SOUTH_GROUP0_UART0_TXD, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB5_GBE_CLK (GPIO_103) + {SOUTH_GROUP0_SMB5_GBE_CLK, + {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // SMB_GBE_DATA (GPIO_104) + {SOUTH_GROUP0_SMB5_GBE_DATA, + {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} }, + // ERROR2_N (GPIO_105) + {SOUTH_GROUP0_ERROR2_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // ERROR1_N (GPIO_106) + {SOUTH_GROUP0_ERROR1_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // ERROR0_N (GPIO_107) + {SOUTH_GROUP0_ERROR0_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // IERR_N (CATERR_N) (GPIO_108) + {SOUTH_GROUP0_IERR_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // MCERR_N (GPIO_109) + {SOUTH_GROUP0_MCERR_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB0_LEG_CLK (GPIO_110) + {SOUTH_GROUP0_SMB0_LEG_CLK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB0_LEG_DATA (GPIO_111) + {SOUTH_GROUP0_SMB0_LEG_DATA, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB0_LEG_ALRT_N (GPIO_112) + {SOUTH_GROUP0_SMB0_LEG_ALRT_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB1_HOST_DATA (GPIO_113) + {SOUTH_GROUP0_SMB1_HOST_DATA, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB1_HOST_CLK (GPIO_114) + {SOUTH_GROUP0_SMB1_HOST_CLK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB2_PECI_DATA (GPIO_115) + {SOUTH_GROUP0_SMB2_PECI_DATA, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB2_PECI_CLK (GPIO_116) + {SOUTH_GROUP0_SMB2_PECI_CLK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB4_CSME0_DATA (GPIO_117) + {SOUTH_GROUP0_SMB4_CSME0_DATA, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB4_CSME0_CLK (GPIO_118) + {SOUTH_GROUP0_SMB4_CSME0_CLK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB4_CSME0_ALRT_N (GPIO_119) + {SOUTH_GROUP0_SMB4_CSME0_ALRT_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // USB_OC0_N (GPIO_120) + {SOUTH_GROUP0_USB_OC0_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // FLEX_CLK_SE0 (GPIO_121) + {SOUTH_GROUP0_FLEX_CLK_SE0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // FLEX_CLK_SE1 (GPIO_122) + {SOUTH_GROUP0_FLEX_CLK_SE1, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // GBE3_LED1 (GPIO_4) + {SOUTH_GROUP0_GPIO_4, + {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB3_IE0_CLK (GPIO_5) + {SOUTH_GROUP0_GPIO_5, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB3_IE0_DATA (GPIO_6) + {SOUTH_GROUP0_GPIO_6, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB3_IE0_ALERT_N (GPIO_7) + {SOUTH_GROUP0_GPIO_7, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SATA0_LED (GPIO_90) + {SOUTH_GROUP0_SATA0_LED_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SATA1_LED (GPIO_91) + {SOUTH_GROUP0_SATA1_LED_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SATA_PDETECT0 (GPIO_92) + {SOUTH_GROUP0_SATA_PDETECT0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SATA_PDETECT1 (GPIO_93) + {SOUTH_GROUP0_SATA_PDETECT1, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // UART1_RTS (GPIO_94) + {SOUTH_GROUP0_SATA0_SDOUT, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // UART1_CTS (GPIO_95) + {SOUTH_GROUP0_SATA1_SDOUT, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // UART1_RXD (GPIO_96) + {SOUTH_GROUP0_UART1_RXD, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // UART1_TXD (GPIO_97) + {SOUTH_GROUP0_UART1_TXD, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB6_CSME1_DATA (GPIO_8) + {SOUTH_GROUP0_GPIO_8, + {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB6_CSME1_CLK (GPIO_9) + {SOUTH_GROUP0_GPIO_9, + {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // TCK (GPIO_141) + {SOUTH_GROUP0_TCK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // TRST_N (GPIO_142) + {SOUTH_GROUP0_TRST_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // TMS (GPIO_143) + {SOUTH_GROUP0_TMS, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // TDI (GPIO_144) + {SOUTH_GROUP0_TDI, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // TDO (GPIO_145) + {SOUTH_GROUP0_TDO, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // CX_PRDY_N (GPIO_146) + {SOUTH_GROUP0_CX_PRDY_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // CX-PREQ_N (GPIO_147) + {SOUTH_GROUP0_CX_PREQ_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // ME_RECVR_HDR (GPIO_148) + {SOUTH_GROUP0_CTBTRIGINOUT, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpu20K /*GpioTermDefault*/, + GpioLockDefault} }, + // ADV_DBG_DFX_HDR (GPIO_149) + {SOUTH_GROUP0_CTBTRIGOUT, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // LAD2_SPI_IRQ_N (GPIO_150) + {SOUTH_GROUP0_DFX_SPARE2, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB_PECI_ALRT_N (GPIO_151) + {SOUTH_GROUP0_DFX_SPARE3, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SMB_CSME1_ALRT_N (GPIO_152) + {SOUTH_GROUP0_DFX_SPARE4, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SUSPWRDNACK (GPIO_79) + {SOUTH_GROUP1_SUSPWRDNACK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PMU_SUSCLK (GPIO_80) + {SOUTH_GROUP1_PMU_SUSCLK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // ADR_TRIGGER_N (GPIO_81) + {SOUTH_GROUP1_ADR_TRIGGER, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PMU_SLP_S45_N (GPIO_82) + {SOUTH_GROUP1_PMU_SLP_S45_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PMU_SLP_S3_N (GPIO_83) + {SOUTH_GROUP1_PMU_SLP_S3_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PMU_WAKE_N (GPIO_84) + {SOUTH_GROUP1_PMU_WAKE_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PMU_PWRBTN_N (GPIO_85) + {SOUTH_GROUP1_PMU_PWRBTN_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PMU_RESETBUTTON_N (GPIO_86) + {SOUTH_GROUP1_PMU_RESETBUTTON_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PMU_PLTRST_N (GPIO_87) + {SOUTH_GROUP1_PMU_PLTRST_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // PMU_SUS_STAT_N (GPIO_88) + {SOUTH_GROUP1_SUS_STAT_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // TDB_CIO_PLUG_EVENT (GPIO_89) + {SOUTH_GROUP1_SLP_S0IX_N, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SPI_CS0_N (GPIO_72) + {SOUTH_GROUP1_SPI_CS0_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SPI_CS1_N (GPIO_73) + {SOUTH_GROUP1_SPI_CS1_N, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SPI_MOSI_IO0 (GPIO_74) + {SOUTH_GROUP1_SPI_MOSI_IO0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SPI_MISO_IO1 (GPIO_75) + {SOUTH_GROUP1_SPI_MISO_IO1, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SPI_IO2 (GPIO_76) + {SOUTH_GROUP1_SPI_IO2, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SPI_IO3 (GPIO_77) + {SOUTH_GROUP1_SPI_IO3, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // SPI_CLK (GPIO_78) + {SOUTH_GROUP1_SPI_CLK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // LPC_AD0 (GPIO_64) + {SOUTH_GROUP1_ESPI_IO0, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // LPC_AD1 (GPIO_65) + {SOUTH_GROUP1_ESPI_IO1, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // LPC_AD2 (GPIO_66) + {SOUTH_GROUP1_ESPI_IO2, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // LPC_AD3 (GPIO_67) + {SOUTH_GROUP1_ESPI_IO3, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // LPC_FRAME_N (GPIO_68) + {SOUTH_GROUP1_ESPI_CS0_N, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // LPC_CLKOUT0 (GPIO_69) + {SOUTH_GROUP1_ESPI_CLK, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // LPC_CLKOUT1 (GPIO_70) + {SOUTH_GROUP1_ESPI_RST_N, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // LPC_CLKRUN_N (GPIO_71) + {SOUTH_GROUP1_ESPI_ALRT0_N, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // MFG_MODE_HDR (GPIO_10) + {SOUTH_GROUP1_GPIO_10, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // LPC_SERIRQ (GPIO_11) + {SOUTH_GROUP1_GPIO_11, + {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // EMMC-CMD (GPIO_123) + {SOUTH_GROUP1_EMMC_CMD, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} }, + // EMMC-CSTROBE (GPIO_124) + {SOUTH_GROUP1_EMMC_STROBE, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, + // EMMC-CLK (GPIO_125) + {SOUTH_GROUP1_EMMC_CLK, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpd20K, GpioLockDefault} }, + // EMMC-D0 (GPIO_126) + {SOUTH_GROUP1_EMMC_D0, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} }, + // EMMC-D1 (GPIO_127) + {SOUTH_GROUP1_EMMC_D1, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} }, + // EMMC-D2 (GPIO_128) + {SOUTH_GROUP1_EMMC_D2, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} }, + // EMMC-D3 (GPIO_129) + {SOUTH_GROUP1_EMMC_D3, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} }, + // EMMC-D4 (GPIO_130) + {SOUTH_GROUP1_EMMC_D4, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} }, + // EMMC-D5 (GPIO_131) + {SOUTH_GROUP1_EMMC_D5, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} }, + // EMMC-D6 (GPIO_132) + {SOUTH_GROUP1_EMMC_D6, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} }, + // EMMC-D7 (GPIO_133) + {SOUTH_GROUP1_EMMC_D7, + {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} }, + // IE_ROM GPIO (GPIO_3) + {SOUTH_GROUP1_GPIO_3, + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, + GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} }, +}; +#endif + +#endif /* _MAINBOARD_GPIO_H */ diff --git a/src/mainboard/qotom/qdnv01/hsio.c b/src/mainboard/qotom/qdnv01/hsio.c new file mode 100644 index 0000000000..3b1beac3ff --- /dev/null +++ b/src/mainboard/qotom/qdnv01/hsio.c @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const BL_HSIO_INFORMATION qdnv01_hsio_config[] = { + /* + * + * Bifurcation: + * PCIE cluster #0: x2x2x2x2 + * PCIE cluster #1: x2x2x2x2 + * + */ + {BL_SKU_HSIO_20, + {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, + {/* ME_FIA_MUX_CONFIG */ + {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE04) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE05) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE06) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE07) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE10) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE11) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)}, + + /* ME_FIA_SATA_CONFIG */ + {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE04) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE05) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE06) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE07) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE08) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE09) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE10) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE11) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE12) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE13) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE14) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE15) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, + BL_FIA_SATA_LANE16) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, + BL_FIA_SATA_LANE17) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, + BL_FIA_SATA_LANE18) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE19)}, + + /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ + {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_0) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_1) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_2) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_3) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_4) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_5) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_6) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_7) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, + BL_FIA_PCIE_ROOT_PORT_0) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, + BL_FIA_PCIE_ROOT_PORT_1) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_2) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_3) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_4) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_5) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_6) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_7)} } }, + + /* SKU HSIO 12 */ + {BL_SKU_HSIO_12, + {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, + {/*ME_FIA_MUX_CONFIG */ + {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) | + BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)}, + + /* ME_FIA_SATA_CONFIG */ + {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE04) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE05) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE06) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE07) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE08) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE09) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE10) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE11) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE12) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE13) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE14) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE15) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, + BL_FIA_SATA_LANE16) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, + BL_FIA_SATA_LANE17) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, + BL_FIA_SATA_LANE18) | + BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, + BL_FIA_SATA_LANE19)}, + + /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ + {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_0) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_1) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_2) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_3) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_4) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_5) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_6) | + BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, + BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, + BL_FIA_PCIE_ROOT_PORT_7) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, + BL_FIA_PCIE_ROOT_PORT_0) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, + BL_FIA_PCIE_ROOT_PORT_1) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_2) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_3) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_4) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_5) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_6) | + BL_FIA_PCIE_ROOT_PORT_CONFIG( + BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, + BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, + BL_FIA_PCIE_ROOT_PORT_7)} } } +}; + +size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) +{ + const size_t num = ARRAY_SIZE(qdnv01_hsio_config); + (*p_hsio_config) = (BL_HSIO_INFORMATION *)qdnv01_hsio_config; + return num; +} diff --git a/src/mainboard/qotom/qdnv01/ramstage.c b/src/mainboard/qotom/qdnv01/ramstage.c new file mode 100644 index 0000000000..b7e56c569d --- /dev/null +++ b/src/mainboard/qotom/qdnv01/ramstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + /* Disable eMMC */ + params->FspsConfig.PcdEnableEmmc = 0; +} diff --git a/src/mainboard/qotom/qdnv01/romstage.c b/src/mainboard/qotom/qdnv01/romstage.c new file mode 100644 index 0000000000..4a2ea2c4e2 --- /dev/null +++ b/src/mainboard/qotom/qdnv01/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "gpio.h" +#include +#include +#include +#include + + +/* +* Configure GPIO depend on platform +*/ +void mainboard_config_gpios(void) +{ + const int num = ARRAY_SIZE(qdnv01_gpio_table); + const struct dnv_pad_config *table = qdnv01_gpio_table; + + printk(BIOS_INFO, "GPIO table: 0x%lx, entry num: %d!\n", + (uintptr_t)table, num); + gpio_configure_dnv_pads(table, num); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* Disable Memory Down function */ + mupd->FspmConfig.PcdMemoryDown = 0; + + mupd->FspmConfig.PcdMmioSize = 2; + + /* Enable memory preservation through warm resets and Fast Boot by default */ + mupd->FspmConfig.PcdMemoryPreservation = 1; + mupd->FspmConfig.PcdFastBoot = 1; + mupd->FspmConfig.PcdSkipMemoryTest = 1; + + /* FSP debug message level */ + mupd->FspmConfig.PcdFspDebugPrintErrorLevel = 1; +}