From 72365c33693db4eb6e01032938221f592b7e5a02 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Fri, 25 Oct 2013 14:11:09 -0700 Subject: [PATCH] tegra124: fix typos in the clock code. Wrong clock for I2C4 and it was not getting set anyway. And, it was breaking I2C3. BUG=None BRANCH=None TEST=Builds with this change. Boots as far as it ever boots for me. But as it is now it's so wrong you really want to pick this one up. Change-Id: I67d8bf0675759497a998a99e31810006a4424c90 Signed-off-by: Ronald G. Minnich Reviewed-on: https://chromium-review.googlesource.com/174684 Reviewed-by: Julius Werner Commit-Queue: Ronald Minnich Tested-by: Ronald Minnich --- src/soc/nvidia/tegra124/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index f1e34577de..7be06fb30c 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -359,7 +359,7 @@ void clock_config(void) /* I2C3 (cam) gets CLK_M and a divisor of 17 */ clock_ll_set_source_divisor(&clk_rst->clk_src_i2c3, 3, 16); /* I2C4 (ddc) gets CLK_M and a divisor of 17 */ - clock_ll_set_source_divisor(&clk_rst->clk_src_i2c3, 4, 16); + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c4, 3, 16); /* I2C5 (PMU) gets CLK_M and a divisor of 17 */ clock_ll_set_source_divisor(&clk_rst->clk_src_i2c5, 3, 16);