diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig new file mode 100644 index 0000000000..698df3c4d0 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/Kconfig @@ -0,0 +1,137 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_SIEMENS_BASEBOARD_MC_RPL + def_bool n + select BOARD_ROMSIZE_KB_32768 + select CPU_INTEL_SOCKET_LGA1700 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_MAX98373 + select DRIVERS_INTEL_DPTF + select DRIVERS_INTEL_MIPI_CAMERA + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_SOUNDWIRE_ALC_BASE_7XX + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS + select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + + +config BOARD_SIEMENS_MC_RPL1 + select BOARD_SIEMENS_BASEBOARD_MC_RPL + select DRIVERS_UART_8250IO + select GEN3_EXTERNAL_CLOCK_BUFFER + select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_RAPTORLAKE + +if BOARD_SIEMENS_BASEBOARD_MC_RPL + +config SOC_INTEL_CSE_LITE_SKU + bool "Use CSE Lite firmware" + default y if MC_RPL_CHROME_EC + help + Enable if CSE Lite firmware is used in your build. It is commonly + used in Chrome boards (chromebooks, chromeboxes, ...). + But since ADL RVP build can be used with or without CSE Lite firmware + it is a configurable option. Alderlake RVP boards usually don't use + an CSE Lite firmware, but are still very likely to use it in case + ChromeEC is used. + +config CHROMEOS + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_ALTFW + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + +config MAINBOARD_DIR + default "siemens/mc_rpl" + +config VARIANT_DIR + default "mc_rpl1" if BOARD_SIEMENS_MC_RPL1 + +config GBB_HWID + string + depends on CHROMEOS + default "ADLRVPN TEST 7673" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC + default "ADLRVPP TEST 2418" + +config MAINBOARD_PART_NUMBER + default "MC RPL1" if BOARD_SIEMENS_MC_RPL1 + +config MAINBOARD_VENDOR + string + default "Siemens" + +config MAINBOARD_FAMILY + string + default "MC RPL" + +config DEVICETREE + default "devicetree.cb" + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +choice + prompt "ON BOARD EC" + default MC_RPL_CHROME_EC if BOARD_SIEMENS_MC_RPL1 + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config MC_RPL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_ACPI + select EC_GOOGLE_CHROMEEC_LPC + +config MC_RPL_INTEL_EC + bool "Intel EC" + select EC_ACPI +endchoice + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC + select EC_GOOGLE_CHROMEEC_SWITCHES if MC_RPL_CHROME_EC + select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_N_EXT_EC + +config UART_FOR_CONSOLE + int + default 0 + +config DRIVER_TPM_SPI_BUS + default 0x2 if BOARD_SIEMENS_MC_RPL1 + +config USE_PM_ACPI_TIMER + default n if BOARD_SIEMENS_MC_RPL1 + +config TPM_TIS_ACPI_INTERRUPT + int + default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC # GPE0_DW2_3 (GPP_E3) + +config GEN3_EXTERNAL_CLOCK_BUFFER + bool + depends on SOC_INTEL_ALDERLAKE_PCH_P + default n + help + Support external Gen-3 clock chip for ADL-P. + `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer + for further distribution to platform. SRCCLKREQB[7:9] maps to internal + SRCCLKREQB[6]. If any of them asserted, SRC buffer + `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled. + +config CLKSRC_FOR_EXTERNAL_BUFFER + depends on GEN3_EXTERNAL_CLOCK_BUFFER + int + default 6 # CLKSRC 6 +endif diff --git a/src/mainboard/siemens/mc_rpl/Kconfig.name b/src/mainboard/siemens/mc_rpl/Kconfig.name new file mode 100644 index 0000000000..8983c9e6d7 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/Kconfig.name @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +comment "MC RPLx" + +config BOARD_SIEMENS_MC_RPL1 + bool "-> MC RPL1" diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk new file mode 100644 index 0000000000..b63953c0e0 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/Makefile.mk @@ -0,0 +1,34 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c +ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) +bootblock-y += early_gpio_n.c +ramstage-y += gpio_n.c +else +bootblock-y += early_gpio.c +ramstage-y += gpio.c +endif + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c +romstage-y += memory.c +ifeq ($(CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC),y) +romstage-y += memory_rpl.c +endif + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += mainboard.c +ramstage-y += board_id.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/mc_rpl/board_id.c b/src/mainboard/siemens/mc_rpl/board_id.c new file mode 100644 index 0000000000..02445f2f3a --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/board_id.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include "board_id.h" + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + static int id = 1; + + return (id & BOARD_ID_MASK); +} diff --git a/src/mainboard/siemens/mc_rpl/board_id.h b/src/mainboard/siemens/mc_rpl/board_id.h new file mode 100644 index 0000000000..2988127e9b --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/board_id.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0d +/* Bit 5:0 for Board ID */ +#define BOARD_ID_MASK 0x3f + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/siemens/mc_rpl/board_info.txt b/src/mainboard/siemens/mc_rpl/board_info.txt new file mode 100644 index 0000000000..1c0d6c8745 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Siemens +Board name: MC RPL +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/siemens/mc_rpl/bootblock.c b/src/mainboard/siemens/mc_rpl/bootblock.c new file mode 100644 index 0000000000..eeee406f12 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + variant_configure_early_gpio_pads(); +} diff --git a/src/mainboard/siemens/mc_rpl/chromeos.c b/src/mainboard/siemens/mc_rpl/chromeos.c new file mode 100644 index 0000000000..4c2d1e516f --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/chromeos.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + }; + if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) || + CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC)) + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); + else + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1); +} + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||\ + CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC)) +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} +#endif diff --git a/src/mainboard/siemens/mc_rpl/chromeos.fmd b/src/mainboard/siemens/mc_rpl/chromeos.fmd new file mode 100644 index 0000000000..0e8d321f85 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/chromeos.fmd @@ -0,0 +1,54 @@ +FLASH 32M { + SI_ALL 6M { + SI_DESC 4K + SI_EC 512K + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1588K + CSE_DATA 512K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 3520K + } + } + SI_BIOS 26M { + RW_SECTION_A 8M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + RW_LEGACY(CBFS) 1M + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 192K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 128K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # This section starts at the 16M boundary in SPI flash. + # ADL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb new file mode 100644 index 0000000000..031b2f059b --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/devicetree.cb @@ -0,0 +1,469 @@ +chip soc/intel/alderlake + + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses. + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + # Sagv Configuration + register "sagv" = "SaGv_Enabled" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable PCH PCIE RP 5 using CLK 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 6 using CLK 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 50, + }" + + # Enable PCH PCIE RP 9 using CLK 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 11 for optane + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + + # Hybrid storage mode + register "hybrid_storage_mode" = "true" + + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + # Enable CPU PCIE RP 2 using CLK 3 + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_req = 3, + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + # Enable CPU PCIE RP 3 using CLK 4 + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_req = 4, + .clk_src = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + register "sata_salp_support" = "1" + + register "sata_ports_enable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + register "sata_ports_dev_slp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + # Enable EDP in PortA + register "ddi_portA_config" = "1" + # Enable HDMI in Port B + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + # TCSS USB3 + register "tcss_aux_ori" = "0" + + register "s0ix_enable" = "true" + register "dptf_enable" = "true" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "serial_io_gspi_cs_mode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "serial_io_gspi_cs_state" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + + register "cnvi_bt_audio_offload" = "true" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref pcie5_0 on end + device ref igpu on end + device ref dtt on + chip drivers/intel/dptf + + ## sensor information + register "options.tsr[0].desc" = ""Ambient"" + register "options.tsr[1].desc" = ""Battery"" + register "options.tsr[2].desc" = ""DDR"" + register "options.tsr[3].desc" = ""Skin"" + + ## Active Policy + # TODO: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 90), + TEMP_PCT(90, 80), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(80, 90), + TEMP_PCT(70, 80), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 35000, + .max_power = 45000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 56000, + .max_power = 56000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "true" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1"" + register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0"" + register "cio2_prt[0]" = "2" + register "cio2_prt[1]" = "1" + device generic 0 on end + end + end + device ref pcie4_0 on end + device ref pcie4_1 on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref crashlog off end + device ref tcss_xhci on end + device ref tcss_dma0 on end + device ref tcss_dma1 on end + device ref xhci on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on end + device ref i2c1 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "true" + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata on end + device ref i2c5 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "true" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp11 on end + device ref uart0 on end + device ref gspi0 on end + device ref p2sb on end + device ref gspi1 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + device spi 0 on end + end + end + device ref hda on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711" + device generic 0.1 on end + end + end + end + end + device ref smbus on end + end +end diff --git a/src/mainboard/siemens/mc_rpl/devicetree_m.cb b/src/mainboard/siemens/mc_rpl/devicetree_m.cb new file mode 100644 index 0000000000..1ee0f324dc --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/devicetree_m.cb @@ -0,0 +1,406 @@ +fw_config + field AUDIO 8 10 + option NONE 0 + option ADL_MAX98373_ALC5682I_I2S 1 + end +end +chip soc/intel/alderlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A port 1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Type-A port 2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN + + # Sagv Configuration + register "sagv" = "SaGv_Enabled" + + # Enable CNVi Bluetooth + register "cnvi_bt_core" = "true" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + #Enable PCH PCIE RP 4 using CLK 5 + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_L1_2, + }" + + # Enable PCH PCIE RP 5 using CLK 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_L1_2, + }" + + # Enable PCH PCIE RP 9 using CLK 3 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_L1_2, + }" + + #Enable PCH PCIE RP 10 using CLK 1 + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_L1_2, + }" + + # Hybrid storage mode + register "hybrid_storage_mode" = "true" + + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + # Enable EDP in PortA + register "ddi_portA_config" = "1" + # Enable HDMI in Port B + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + # TCSS USB3 + register "tcss_aux_ori" = "0" + + register "s0ix_enable" = "true" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "serial_io_gspi_cs_mode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "serial_io_gspi_cs_state" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref pcie5_0 on end + device ref igpu on end + device ref dtt on end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1"" + register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0"" + register "cio2_prt[0]" = "2" + register "cio2_prt[1]" = "1" + device generic 0 on end + end + end + device ref pcie4_0 on end + device ref pcie4_1 on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tcss_xhci on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TypeC Port 1"" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""TypeC Port 2"" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref tcss_dma0 on end + device ref xhci on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_H3_IRQ)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO ADL_MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO ADL_MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO ADL_MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/hid + register "generic.hid" = ""WACOM PWB-D893"" + register "generic.desc" = ""WACOM Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_delay_ms" = "300" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0a on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0000"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D11_IRQ)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H1)" + register "generic.wake" = "GPE0_DW1_11" + register "generic.detect" = "1" + register "generic.has_power_resource" = "1" + device i2c 15 on end + end + end + device ref i2c1 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "true" + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata on end + device ref i2c5 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "true" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + end + device ref pcie_rp1 on end + device ref pcie_rp3 on end # W/A to FSP issue + device ref pcie_rp4 on end # W/A to FSP issue + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref uart0 on end + device ref gspi0 on end + device ref p2sb on end + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + device spi 0 on end + end + end # GSPI1 + device ref hda on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711" + device generic 0.1 on end + end + end + end + end + device ref smbus on end + end +end diff --git a/src/mainboard/siemens/mc_rpl/devicetree_n.cb b/src/mainboard/siemens/mc_rpl/devicetree_n.cb new file mode 100644 index 0000000000..1eff9459d3 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/devicetree_n.cb @@ -0,0 +1,403 @@ +chip soc/intel/alderlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + # Sagv Configuration + register "sagv" = "SaGv_Enabled" + + # Enable DPTF + register "dptf_enable" = "true" + + # eMMC HS400 + register "emmc_enable_hs400_mode" = "true" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port3 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type A/ M.2 WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable PCH PCIE RP 7 using CLK 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 9 using CLK 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + register "sata_salp_support" = "0" + + # Enable EDP in PortA + register "ddi_portA_config" = "1" + # Enable HDMI in Port B + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + # TCSS USB3 + register "tcss_aux_ori" = "4" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}" + + register "s0ix_enable" = "true" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "serial_io_gspi_cs_mode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "serial_io_gspi_cs_state" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + + register "cnvi_bt_audio_offload" = "true" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + device domain 0 on + device ref igpu on end + device ref dtt on + chip drivers/intel/dptf + + ## sensor information + register "options.tsr[0].desc" = ""Ambient"" + register "options.tsr[1].desc" = ""Battery"" + register "options.tsr[2].desc" = ""DDR"" + register "options.tsr[3].desc" = ""Skin"" + register "options.tsr[4].desc" = ""VR"" + + ## Active Policy + # TODO: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 90), + TEMP_PCT(90, 80), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(80, 90), + TEMP_PCT(70, 80), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000), + [5] = DPTF_PASSIVE(CPU, TEMP_SENSOR_4, 85, 50000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN), + [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 95, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 25000, + .max_power = 35000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "true" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1"" + register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0"" + register "cio2_prt[0]" = "2" + register "cio2_prt[1]" = "1" + device generic 0 on end + end + end + device ref crashlog off end + device ref tcss_xhci on end + device ref xhci on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on end + device ref i2c1 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "true" + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata off end + device ref i2c5 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "true" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + end + device ref pcie_rp7 on end + device ref pcie_rp9 on end + device ref uart0 on end + device ref gspi0 on end + device ref p2sb on end + device ref emmc on end + device ref ish on end + device ref ufs on end + device ref hda on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711" + device generic 0.1 on end + end + end + end + end + device ref smbus on end + end +end diff --git a/src/mainboard/siemens/mc_rpl/dsdt.asl b/src/mainboard/siemens/mc_rpl/dsdt.asl new file mode 100644 index 0000000000..f379610866 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/dsdt.asl @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) { + #include + #include + #include + } + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* ChromeOS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } +#endif + + #include +} diff --git a/src/mainboard/siemens/mc_rpl/early_gpio.c b/src/mainboard/siemens/mc_rpl/early_gpio.c new file mode 100644 index 0000000000..c3b2e2a47c --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/early_gpio.c @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# (updated in ramstage) */ + PAD_CFG_GPO(GPP_F14, 0, DEEP), + /* WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + /* WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F15, 0, DEEP), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + + /* x4 PCIE slot 1 RESET */ + PAD_CFG_GPO(GPP_F10, 0, PLTRST), + + /* Support external source clock via OEB6 and OEB7 */ + /* SRCCLK_OEB6 for built-in LAN */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF2), + /* SRCCLK_OEB7 for x4 slot */ + PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1), + + /* CPU PCIe VGPIO for RP0 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, PLTRST, NF1), + + /* CPU PCIe vGPIO for RP1 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, PLTRST, NF1), + + /* CPU PCIe vGPIO for RP2 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1), + + /* CPU PCIe vGPIO for RP3 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), + + /*_TPM_*/ + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + /* F16 : GSPI1_CS0N */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + /* F11 : GSPI1_CLK */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + /* F13 : GSPI1_MISO */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + /* F12 : GSPI1_MOSI */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), +}; + +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +void variant_configure_early_gpio_pads(void) +{ + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/siemens/mc_rpl/early_gpio_m.c b/src/mainboard/siemens/mc_rpl/early_gpio_m.c new file mode 100644 index 0000000000..fbc6467b46 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/early_gpio_m.c @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + + /* H0 : PCH_SSD_RST# */ + PAD_CFG_GPO(GPP_H0, 0, PLTRST), + /* H13 : CPU_SSD_RST# */ + PAD_CFG_GPO(GPP_H13, 0, PLTRST), + + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + + /* CPU PCIe VGPIO for RP0 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP1 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP2 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP3 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), + + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + /* TPM */ + /* F16 : GSPI1_CS0N */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + /* F11 : GSPI1_CLK */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + /* F13 : GSPI1_MISO */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + /* F12 : GSPI1_MOSI */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + + /* D10 : PCH_SSD_PWR_EN */ + PAD_CFG_GPO(GPP_D10, 1, PLTRST), + /* D16 : CPU_SSD_PWR_EN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + +}; + +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +void variant_configure_early_gpio_pads(void) +{ + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/siemens/mc_rpl/early_gpio_n.c b/src/mainboard/siemens/mc_rpl/early_gpio_n.c new file mode 100644 index 0000000000..3eb1ceae52 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/early_gpio_n.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), +}; + +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +void variant_configure_early_gpio_pads(void) +{ + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/siemens/mc_rpl/ec.c b/src/mainboard/siemens/mc_rpl/ec.c new file mode 100644 index 0000000000..14760017ef --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/siemens/mc_rpl/fw_config.c b/src/mainboard/siemens/mc_rpl/fw_config.c new file mode 100644 index 0000000000..8589bd8bdc --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/fw_config.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct pad_config i2s_enable_pads[] = { + /* Audio Codec INT N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, EDGE_BOTH, INVERT), + + /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* I2S0_TXD */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* I2S0_RXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + + /* I2S2_SCLK */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), + /* I2S2_SFRM */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* I2S2_TXD */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* I2S2_RXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +}; + +static void fw_config_handle(void *unused) +{ + if (fw_config_probe(FW_CONFIG(AUDIO, ADL_MAX98373_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/siemens/mc_rpl/gpio.c b/src/mainboard/siemens/mc_rpl/gpio.c new file mode 100644 index 0000000000..d1ed7c7df1 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/gpio.c @@ -0,0 +1,276 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when + eSPI is enabled */ + + /* SSD1_PWREN CPU SSD1 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* SSD1_RESET CPU SSD1 */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* WLAN RST# */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* WIFI_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT), + /* x4 PCIE slot1 PWREN */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + /* x4 PCIE slot 1 RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* Retimer Force Power */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + /* PEG Slot RST# */ + PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* M.2 SSD_2 Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* Audio Codec INT N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* THC1 SPI2 RST# */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + /* WWAN WAKE N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), + /* WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_F15, 1, DEEP), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), + /* WWAN_PERST# */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + /* PEG_SLOT_WAKE_N */ + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), + /* CAM CONN1 CLKEN */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* CPU SSD2 PWREN */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* CPU SSD2 RST# */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* Sata direct Power */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + /* M.2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + + /* CAM1_RST */ + PAD_CFG_GPO(GPP_R5, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* THC0 SPI1 CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), + /* THC0 SPI1 IO 1 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), + /* THC0 SPI1 IO 2 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), + /* THC0 SPI IO 3 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), + /* THC1 SPI1 RSTB */ + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2), + /* UART_RX(1) */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* UART_RX(2) */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* UART_RX(4) */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + /* UART_RX(5) */ + PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1), + /* UART_RX(6) */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1), + + /* UART_TX(1) */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* UART_TX(2) */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* UART_TX(4) */ + PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), + /* UART_TX(5) */ + PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1), + /* UART_TX(6) */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1), + + /* UART_RTS(1) */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* UART_RTS(2) */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* UART_RTS(4) */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + /* UART_RTS(5) */ + PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1), + /* UART_RTS(6) */ + PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1), + + /* UART_CTS(1) */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* UART_CTS(2) */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + /* UART_CTS(4) */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + /* UART_CTS(5) */ + PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1), + /* UART_CTS(6) */ + PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1), + + /* SPI_MOSI(1) */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* SPI_MOSI(2) */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + + /* SPI_MIS0(1) */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* SPI_MIS0(2) */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + + /* SPI_CLK(1) */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* SPI_CLK(2) */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + + /* SPI_CS(0, 1) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* SPI_CS(1, 0) */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* SPI_CS(2, 0) */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* I2C_SCL(5) */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* I2C_SDA(5) */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + + /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* I2S0_TXD */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* I2S0_RXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + + /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* I2S_MCLK2_INOUT */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW1_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW2_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* SNDW2_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* SNDW3_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* SNDW4_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* SNDW4_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* SATA DEVSLP */ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), + + /* SATA LED pin */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* USB2 OC0 pins */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* USB2 OC3 pins */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPIO pin for PCIE SRCCLKREQB */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_NC(GPP_D8, NONE), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + + /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + + /* HPD_1 (E14) and HPD_2 (A18) pins */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : CLKREQ5_WWAN_N */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + + /* A21 : HDMI CRLS CTRLCLK */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + /* A22 : HDMI CRLS CTRLDATA */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT) +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/siemens/mc_rpl/gpio_m.c b/src/mainboard/siemens/mc_rpl/gpio_m.c new file mode 100644 index 0000000000..5d2366858e --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/gpio_m.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A12 : BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + + /* H2 : WLAN_RST_N */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* 8 : M.2_BTWIFI_SUS_CLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* 9 : GPD_9_SLP_WLAN_N */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* 10 : GPD_10_SLP_S5_N */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + + /* D12 : WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_D12, 1, PLTRST), + /* D13 : WIFI_WAKE_N */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : x1 PCIE slot1 PWREN / SML0B_CLK */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* D17 : PCIE SLOT1 WAKE N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, DEEP, LEVEL, INVERT), + /* D18 : WWAN WAKE N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), + /* H23 : CLKREQ5_WWAN_N */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), + + /* F0 : CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP_BT_UART2_RXD */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + /* F2 : CNV_RGI_DT_BT_UART2_TXD */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + /* F4 : CNV_RF_RESET_R_N */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ_R */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* F6 : GPPC_F6_CNV_PA_BLANKING */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F10 : GPPC_F10 X1_Slot_RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* H8 : CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + + /* A14 : TCPC01_TYPEA23_OC1_N */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_TYPEA_OC2_N */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* E18 : TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : TBT_LSX1_TXD */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : TBT_LSX1_RXD */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + + /* H4 : I2C0 SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H6 : I2C1 SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* B16 : I2C5 SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + + /* H5 : I2C0 SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H7 : I2C1 SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* B17 : I2C5 SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + + /* C5 : WWAN_PERST_N */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* E5 : WWAN_PERST# */ + PAD_CFG_GPO(GPP_E5, 1, PLTRST), + /* D15 : WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* D9 : WWAN_FCP_POWER_OFF_N */ + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + + /* H0 : PCH_SSD_RST# */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* H13 : CPU_SSD_RST# */ + PAD_CFG_GPO(GPP_H13, 1, PLTRST), + + /* DDP1/2/A/B CTRLCLK and CTRLDATA pins */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* HPD_1 (E14) and HPD_2 (A18) pins */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + + /* GPIO pin for PCIE SRCCLKREQB */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + + /* CAM1_RST */ + PAD_CFG_GPO(GPP_R5, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), + /* IMGCLKOUT0 */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + /* IMGCLKOUT1 */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + + /* C16 : I2C0 SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + + /* S0 : SNDW1_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + + /* S1 : SNDW1_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + + /* S2 : SNDW2_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + + /* S3 : SNDW2_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + + /* S4 : SNDW3_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + + /* S5 : SNDW3_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + + /* S6 : SNDW4_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + + /* S7 : SNDW4_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* F7 : TCH_PNL_PWR_EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* F17 : RST_N_TCH_PNL2 */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + /* F18 : INT_N_TCH_PNL2 */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE), + + /* E3 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + + /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_E4, 0, DEEP), + + /* H1 : GPPC_H1_TCH_PAD_TCH_PNL2_LS_EN */ + PAD_CFG_GPO(GPP_H1, 0, PLTRST), + + /* D11 : TCH_PAD_INT_N */ + PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST, LEVEL, INVERT) +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/siemens/mc_rpl/gpio_n.c b/src/mainboard/siemens/mc_rpl/gpio_n.c new file mode 100644 index 0000000000..b985d53dd2 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/gpio_n.c @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* ESPI_IO0_EC_R / ESPI_IO0_HDR */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + /* ESPI_IO1_EC_R / ESPI_IO1_HDR */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + /* ESPI_IO2_EC_R / ESPI_IO2_HDR */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + /* ESPI_IO3_EC_R / ESPI_IO3_HDR */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + /* ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + /* ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + /* ESPI_CLK_EC_R / ESPI_CLK_HDR */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* ESPI_RST_EC_R_N / ESPI_RST_HDR_N */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), + + /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* CLKREQ0_M2_SSD_N */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* M2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* M2_SSD_RST_N */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* M2_SSD_DEVSLP */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), + + /* I5 : NC */ + PAD_NC(GPP_I5, NONE), + /* I7 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + /* I8 : EMMC_DATA0 ==> EMMC_D0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + /* I9 : EMMC_DATA1 ==> EMMC_D1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + /* I10 : EMMC_DATA2 ==> EMMC_D2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + /* I11 : EMMC_DATA3 ==> EMMC_D3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + /* I12 : EMMC_DATA4 ==> EMMC_D4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + /* I13 : EMMC_DATA5 ==> EMMC_D5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + /* I14 : EMMC_DATA6 ==> EMMC_D6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + /* I15 : EMMC_DATA7 ==> EMMC_D7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + /* I16 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + /* I17 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + /* I18 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* TYPEA_CONN23_USB2_P8_OC1_N */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* CRD1_PWREN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* TCP1_DISP_AUX_P_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E20, 1, PLTRST), + /* TCP1_DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), + /* TCP0_DISP_AUX_P_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E22, 0, PLTRST), + /* TCP0_DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + + /* EDP1_HPD_MIPI_PNL_RST */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* X1_SLOT_PWREN */ + PAD_CFG_GPO(GPP_A8, 0, PLTRST), + /* SML0_CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* SML0_DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* CLKREQ3_X1PCIE_SLOT_N */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* X1_PCIE_SLOT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D11, NONE, DEEP, LEVEL, INVERT), + /* X1_Slot_RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + + /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* CLKREQ1_WWAN_N */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* GPPC_D15_M.2_WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* WWAN_PWREN */ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* WWAN WAKE N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), //TODO SCI + /* SRCCLK_OEB6 */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF3), + /* GPPC_F6_CNV_PA_BLANKING */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 1, PLTRST), + /* WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_F15, 1, PLTRST), + /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + + /* PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* PM_SLP_DRAM_N */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), + /* CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* CODEC_INT_N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* SNDW0_CLK_HDR */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW0_DATA_HDR */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW1_CLK_DMIC_CLK_A_0 */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* SNDW1_DATA_DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* SNDW2_CLK_R */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* SNDW2_DATA_R */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* SOC_DMIC0_SNDW3_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* SOC_DMIC0_SNDW3_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /* DDIB_DP_HDMI_ALS_HDP */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* 8 : M.2_BTWIFI_SUS_CLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* 9 : GPD_9_SLP_WLAN_N */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + + /* GPIO pin for PCIE SRCCLKREQB_2 */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + /* H2 : WLAN_RST_N */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* CAM_PRIVACY_LED */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + + /* B16 : I2C5 SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* B17 : I2C5 SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* CAM1_RST_N */ + PAD_CFG_GPO(GPP_A21, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* D13 : WIFI_WAKE_N */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + + /* F0 : CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP_BT_UART2_RXD */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + /* F2 : CNV_RGI_DT_BT_UART2_TXD */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + /* F4 : CNV_RF_RESET_R_N */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ_R */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + + /* UART_BT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/ec.h b/src/mainboard/siemens/mc_rpl/include/baseboard/ec.h new file mode 100644 index 0000000000..6a5c72ceeb --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/include/baseboard/ec.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or AC connect/disconnect or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h b/src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h new file mode 100644 index 0000000000..9a1c5851c0 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include +#include + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#define GPIO_EC_IN_RW GPP_E7 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h b/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h new file mode 100644 index 0000000000..bb2c3f62b0 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include +#include +#include + +enum adl_boardid { + /* ADL-P LPDDR4 RVPs */ + ADL_P_LP4_1 = 0x10, + ADL_P_LP4_2 = 0x11, + /* ADL-P DDR5 RVPs */ + ADL_P_DDR5_1 = 0x12, + ADL_P_DDR5_2 = 0x16, + /* ADL-P LPDDR5 RVP */ + ADL_P_LP5_1 = 0x13, + ADL_P_LP5_2 = 0x17, + /* ADL-P DDR4 RVPs */ + ADL_P_DDR4_1 = 0x14, + ADL_P_DDR4_2 = 0x3F, + /* ADL-M LP4 and LP5 RVPs */ + ADL_M_LP4 = 0x1, + ADL_M_LP5 = 0x2, + /* ADL-N LP5 RVP */ + ADL_N_LP5 = 0x7, +}; + +/* Functions to configure GPIO as per variant schematics */ +void variant_configure_gpio_pads(void); +void variant_configure_early_gpio_pads(void); + +size_t variant_memory_sku(void); +const struct mb_cfg *variant_memory_params(void); +void rpl_memory_params(FSPM_UPD *memupd); + +/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); +struct cpu_power_limits { + uint16_t mchid; + u8 cpu_tdp; + unsigned int pl1_min_power; + unsigned int pl1_max_power; + unsigned int pl2_min_power; + unsigned int pl2_max_power; + unsigned int pl4_power; +}; +/* Modify Power Limit devictree settings during ramstage */ +void variant_update_power_limits(void); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c new file mode 100644 index 0000000000..c02cbf9a58 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/mainboard.c @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board_id.h" + +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; + uint8_t sku_id = get_board_id(); + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} + +static void mainboard_init(void *chip_info) +{ + variant_configure_gpio_pads(); + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + mainboard_ec_init(); + + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + +#if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) +static void add_fw_config_oem_string(const struct fw_config *config, void *arg) +{ + struct smbios_type11 *t; + char buffer[64]; + + t = (struct smbios_type11 *)arg; + + snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name); + t->count = smbios_add_string(t->eos, buffer); +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + fw_config_for_each_found(add_fw_config_oem_string, t); +} +#endif + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) + dev->ops->get_smbios_strings = mainboard_smbios_strings; +#endif +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; + +const char *mainboard_vbt_filename(void) +{ + if (!CONFIG(CHROMEOS)) + return "vbt.bin"; + + uint32_t cpu_id = cpu_get_cpuid(); + uint8_t sku_id = get_board_id(); + switch (sku_id) { + case ADL_P_LP5_1: + case ADL_P_LP5_2: + if (cpu_id == CPUID_RAPTORLAKE_J0) + return "vbt_adlrvp_rpl_lp5.bin"; + return "vbt_adlrvp_lp5.bin"; + case ADL_P_DDR5_1: + case ADL_P_DDR5_2: + return "vbt_adlrvp_ddr5.bin"; + default: + return "vbt.bin"; + } +} diff --git a/src/mainboard/siemens/mc_rpl/memory.c b/src/mainboard/siemens/mc_rpl/memory.c new file mode 100644 index 0000000000..160059921b --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/memory.c @@ -0,0 +1,381 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "board_id.h" + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistor */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 50, 20, 25, 25, 25 }, + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +static const struct mb_cfg lpddr4_mem_config = { + .type = MEM_TYPE_LP4X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 2, 3, 1, 6, 7, 5, 4, }, + .dq1 = { 10, 8, 11, 9, 14, 12, 13, 15, }, + }, + .ddr1 = { + .dq0 = { 12, 8, 14, 10, 11, 13, 15, 9, }, + .dq1 = { 5, 0, 7, 3, 6, 2, 1, 4, }, + }, + .ddr2 = { + .dq0 = { 3, 0, 2, 1, 6, 5, 4, 7, }, + .dq1 = { 12, 13, 14, 15, 10, 9, 8, 11, }, + }, + .ddr3 = { + .dq0 = { 2, 6, 7, 1, 3, 4, 0, 5, }, + .dq1 = { 9, 13, 8, 15, 14, 11, 12, 10, }, + }, + .ddr4 = { + .dq0 = { 3, 0, 1, 2, 7, 4, 6, 5, }, + .dq1 = { 10, 8, 11, 9, 14, 13, 12, 15, }, + }, + .ddr5 = { + .dq0 = { 10, 12, 14, 8, 9, 13, 15, 11, }, + .dq1 = { 3, 7, 6, 2, 0, 4, 5, 1, }, + }, + .ddr6 = { + .dq0 = { 12, 15, 14, 13, 9, 10, 11, 8, }, + .dq1 = { 7, 4, 6, 5, 0, 1, 3, 2, }, + }, + .ddr7 = { + .dq0 = { 0, 2, 4, 3, 1, 6, 7, 5, }, + .dq1 = { 13, 9, 10, 11, 8, 12, 14, 15, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, + .dq1 = { 15, 14, 12, 13, 8, 9, 10, 11, }, + }, + .ddr1 = { + .dq0 = { 0, 2, 3, 1, 5, 7, 4, 6, }, + .dq1 = { 14, 13, 15, 12, 8, 9, 11, 10, }, + }, + .ddr2 = { + .dq0 = { 1, 2, 0, 3, 4, 6, 5, 7, }, + .dq1 = { 15, 13, 12, 14, 9, 10, 8, 11, }, + }, + .ddr3 = { + .dq0 = { 2, 1, 3, 0, 7, 4, 5, 6, }, + .dq1 = { 13, 12, 15, 14, 9, 11, 8, 10, }, + }, + .ddr4 = { + .dq0 = { 1, 2, 3, 0, 6, 4, 5, 7, }, + .dq1 = { 15, 13, 14, 12, 10, 9, 8, 11, }, + }, + .ddr5 = { + .dq0 = { 1, 0, 3, 2, 6, 7, 4, 5, }, + .dq1 = { 14, 12, 15, 13, 8, 9, 10, 11, }, + }, + .ddr6 = { + .dq0 = { 0, 2, 1, 3, 4, 7, 5, 6, }, + .dq1 = { 12, 13, 15, 14, 9, 11, 10, 8, }, + }, + .ddr7 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, + .dq1 = { 13, 15, 11, 12, 10, 9, 14, 8, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .LpDdrDqDqsReTraining = 1, + + .UserBd = BOARD_TYPE_MOBILE, + + .lp5x_config = { + .ccc_config = 0xff, + }, +}; + +static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistor */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 50, 30, 30, 30, 27 }, + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + + .ddr_config = { + .dq_pins_interleaved = false, + } +}; + +static const struct mb_cfg adlm_lp4_mem_config = { + .type = MEM_TYPE_LP4X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 13, 12, 14, 8, 11, 10, 9, 15, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 3, 2, 7, 6, 0, 1, 5, 4, }, /* DDR0_DQ1[7:0] */ + }, + .ddr1 = { + .dq0 = { 11, 15, 10, 9, 12, 8, 14, 13, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 0, 1, 7, 6, 2, 5, 4, 3, }, /* DDR1_DQ1[7:0] */ + }, + .ddr2 = { + .dq0 = { 6, 7, 3, 2, 0, 4, 1, 5, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 14, 8, 13, 12, 11, 9, 10, 15, }, /* DDR2_DQ1[7:0] */ + }, + .ddr3 = { + .dq0 = { 2, 6, 7, 3, 1, 5, 0, 4, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */ + }, + .ddr4 = { + .dq0 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */ + .dq1 = { 1, 0, 5, 4, 6, 2, 3, 7, }, /* DDR4_DQ1[7:0] */ + }, + .ddr5 = { + .dq0 = { 8, 10, 9, 12, 14, 11, 13, 15, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 0, 7, 2, 6, 3, 1, 4, 5, }, /* DDR5_DQ1[7:0] */ + }, + .ddr6 = { + .dq0 = { 14, 12, 9, 8, 15, 10, 13, 11, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 4, 0, 5, 6, 3, 2, 1, 7, }, /* DDR6_DQ1[7:0] */ + }, + .ddr7 = { + .dq0 = { 10, 15, 12, 11, 9, 14, 13, 8, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 7, 1, 2, 3, 6, 0, 5, 4, }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0 } + }, + + .ect = true, /* Early Command Training */ + + .CmdMirror = 0xCC, + + .LpDdrDqDqsReTraining = 1, + + .UserBd = BOARD_TYPE_ULT_ULX_T4, +}; + +static const struct mb_cfg adlm_lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 4, 5, 7, 6, 3, 2, 1, 0, }, + .dq1 = { 12, 10, 8, 15, 11, 9, 14, 13, }, + }, + .ddr1 = { + .dq0 = { 1, 0, 2, 3, 7, 4, 5, 6, }, + .dq1 = { 14, 15, 10, 11, 13, 12, 8, 9, }, + }, + .ddr2 = { + .dq0 = { 7, 4, 2, 0, 3, 1, 6, 5, }, + .dq1 = { 14, 13, 15, 12, 8, 9, 10, 11, }, + }, + .ddr3 = { + .dq0 = { 3, 2, 0, 1, 7, 5, 6, 4, }, + .dq1 = { 12, 14, 15, 13, 11, 8, 10, 9, }, + }, + .ddr4 = { + .dq0 = { 2, 3, 0, 1, 6, 4, 7, 5, }, + .dq1 = { 14, 9, 11, 13, 12, 8, 15, 10, }, + }, + .ddr5 = { + .dq0 = { 4, 7, 3, 1, 5, 2, 6, 0, }, + .dq1 = { 14, 8, 11, 9, 12, 15, 10, 13, }, + }, + .ddr6 = { + .dq0 = { 10, 11, 13, 9, 15, 12, 8, 14, }, + .dq1 = { 2, 4, 7, 0, 6, 3, 5, 1, }, + }, + .ddr7 = { + .dq0 = { 13, 15, 11, 14, 10, 12, 8, 9, }, + .dq1 = { 6, 5, 4, 7, 3, 1, 2, 0, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0 } + }, + + .ect = false, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX_T4, + + .lp5x_config = { + .ccc_config = 0xff, + }, +}; + +static const struct mb_cfg adln_lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, + + .LpDdrDqDqsReTraining = 1, + + .lp5x_config = { + .ccc_config = 0xff, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + int board_id = get_board_id(); + + switch (board_id) { + case ADL_P_LP4_1: + case ADL_P_LP4_2: + return &lpddr4_mem_config; + case ADL_P_DDR4_1: + case ADL_P_DDR4_2: + return &ddr4_mem_config; + case ADL_P_DDR5_1: + case ADL_P_DDR5_2: + return &ddr5_mem_config; + case ADL_P_LP5_1: + case ADL_P_LP5_2: + return &lp5_mem_config; + case ADL_M_LP4: + return &adlm_lp4_mem_config; + case ADL_M_LP5: + return &adlm_lp5_mem_config; + case ADL_N_LP5: + return &adln_lp5_mem_config; + default: + die("unsupported board id : 0x%x\n", board_id); + } +} diff --git a/src/mainboard/siemens/mc_rpl/memory_rpl.c b/src/mainboard/siemens/mc_rpl/memory_rpl.c new file mode 100644 index 0000000000..8302a06d1f --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/memory_rpl.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "board_id.h" + +void rpl_memory_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + + int board_id = get_board_id(); + + switch (board_id) { + case ADL_P_LP4_1: + case ADL_P_LP4_2: + case ADL_P_DDR4_1: + case ADL_P_DDR4_2: + case ADL_P_DDR5_1: + case ADL_P_DDR5_2: + default: + return; + case ADL_P_LP5_1: + case ADL_P_LP5_2: + mem_cfg->Lp5BankMode = 1; + return; + } +} diff --git a/src/mainboard/siemens/mc_rpl/ramstage.c b/src/mainboard/siemens/mc_rpl/ramstage.c new file mode 100644 index 0000000000..fd8e20332b --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/ramstage.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board_id.h" +#include + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, PL4 */ + /* PL2 values are for performance configuration */ + { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000, 140000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000, 140000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 }, + { PCI_DID_INTEL_ADL_N_ID_1, 15, 3000, 15000, 35000, 35000, 83000 }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_4, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, 3000, 6000, 25000, 25000, 78000 }, +}; + +WEAK_DEV_PTR(dptf_policy); +void variant_update_power_limits(void) +{ + const struct device *policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = config_of(policy_dev); + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + u8 tdp = get_cpu_tdp(); + + for (size_t i = 0; i < ARRAY_SIZE(limits); i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + struct dptf_power_limits *settings = &config->controls.power_limits; + config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config = conf->power_limits_config; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + MILLIWATTS_TO_WATTS); + printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power, + limits[i].pl4_power); + } + } +} + +static const struct typec_aux_bias_pads pad_config = { GPP_E23, GPP_E22 }; + +static const struct board_id_iom_port_config { + int board_id; + enum typec_port_index port; +} port_config[] = { + { ADL_P_LP4_1, TYPE_C_PORT_2 }, + { ADL_P_LP4_2, TYPE_C_PORT_2 }, + { ADL_P_DDR4_1, TYPE_C_PORT_2 }, + { ADL_P_DDR4_2, TYPE_C_PORT_2 }, + { ADL_P_LP5_1, TYPE_C_PORT_2 }, + { ADL_P_LP5_2, TYPE_C_PORT_2 }, + { ADL_M_LP4, TYPE_C_PORT_1 }, + { ADL_M_LP5, TYPE_C_PORT_0 }, +}; + +static void variant_update_typec_init_config(void) +{ + /* Skip filling aux bias gpio pads for Windows SKUs */ + if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))) + return; + + config_t *config = config_of_soc(); + int board_id = get_board_id(); + for (int i = 0; i < ARRAY_SIZE(port_config); i++) { + if (board_id != port_config[i].board_id) + continue; + + memcpy(&config->typec_aux_bias_pads[port_config[i].port], &pad_config, + sizeof(pad_config)); + } +} + +void variant_devtree_update(void) +{ + variant_update_power_limits(); + variant_update_typec_init_config(); +} diff --git a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c new file mode 100644 index 0000000000..46640b6aad --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "board_id.h" + +#define SPD_ID_MASK 0x7 + +static size_t get_spd_index(void) +{ + uint8_t board_id = get_board_id(); + size_t spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + spd_index = board_id & SPD_ID_MASK; + + printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index); + return spd_index; +} + +/* + * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's + * 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are + * connected on the platform, an external differential buffer chip needs to be placed at + * the platform level. + * + * GEN3_EXTERNAL_CLOCK_BUFFER Kconfig is selected for ADL-P RVP (not applicable for + * ADL-M/N RVP) + * + * CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete + * buffer for further distribution to platform. + */ +static void configure_external_clksrc(FSP_M_CONFIG *m_cfg) +{ + for (unsigned int i = CONFIG_MAX_PCIE_CLOCK_SRC; i < CONFIG_MAX_PCIE_CLOCK_REQ; i++) + m_cfg->PcieClkSrcUsage[i] = CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER; +} + +__weak void rpl_memory_params(FSPM_UPD *memupd) +{ +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; + const struct mb_cfg *mem_config = variant_memory_params(); + int board_id = get_board_id(); + + /* + * Set Raptor Lake specific new upds that Alder Lake doesn't have. + * This can be removed when Alder Lake and Raptor Lake FSP headers align. + */ + rpl_memory_params(memupd); + + /* + * Alder Lake common meminit block driver considers bus width to be 128-bit and + * populates the meminit data accordingly. Alder Lake-N has single memory controller + * with 64-bit bus width. By setting half_populated to true, only the bottom half is + * populated. + * TODO: Implement __weak variant_is_half_populated(void) function. + */ + const bool half_populated = (CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) + || CONFIG(BOARD_INTEL_ADLRVP_N)); + + const struct mem_spd memory_down_spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = get_spd_index(), + }; + + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + .addr_dimm[1] = 0x51, + }, + [1] = { + .addr_dimm[0] = 0x52, + .addr_dimm[1] = 0x53, + }, + }, + }; + + switch (board_id) { + case ADL_P_DDR4_1: + case ADL_P_DDR4_2: + case ADL_P_DDR5_1: + memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated); + break; + case ADL_P_DDR5_2: + case ADL_P_LP4_1: + case ADL_P_LP4_2: + case ADL_P_LP5_1: + case ADL_P_LP5_2: + case ADL_M_LP4: + case ADL_M_LP5: + case ADL_N_LP5: + memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated); + break; + default: + die("Unknown board id = 0x%x\n", board_id); + break; + } + + if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER)) + configure_external_clksrc(m_cfg); +} diff --git a/src/mainboard/siemens/mc_rpl/smihandler.c b/src/mainboard/siemens/mc_rpl/smihandler.c new file mode 100644 index 0000000000..a3b43231ec --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/smihandler.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void mainboard_smi_espi_handler(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} diff --git a/src/mainboard/siemens/mc_rpl/spd/Makefile.mk b/src/mainboard/siemens/mc_rpl/spd/Makefile.mk new file mode 100644 index 0000000000..f503b6d959 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/spd/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = adlrvp_lp4 # 0b000 +SPD_SOURCES += empty # 0b001 +SPD_SOURCES += empty # 0b002 +SPD_SOURCES += adlrvp_lp5 # 0b003 +SPD_SOURCES += empty # 0b004 +SPD_SOURCES += empty # 0b005 +SPD_SOURCES += adlrvp_ddr5_mr # 0b006 +SPD_SOURCES += adlrvp_n_lp5 # 0b007 diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex new file mode 100644 index 0000000000..80ef521cfa --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex @@ -0,0 +1,32 @@ +30 08 12 03 04 00 20 62 00 00 00 00 60 00 00 00 +00 00 00 00 A1 01 E8 03 72 15 00 00 00 00 1E 41 +1E 41 1E 41 00 7D 1E BE 30 75 27 01 A0 00 82 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 47 AE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +08 00 C2 C4 80 00 80 B3 80 11 00 00 00 00 00 00 +00 00 80 B3 80 11 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 0F 10 00 01 01 22 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 9C AD +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex new file mode 100644 index 0000000000..e1d338edbc --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex new file mode 100644 index 0000000000..2f2a31a33d --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A 95 08 00 40 00 00 02 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex new file mode 100644 index 0000000000..88a1f1f473 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 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0000000000..67b46cd239 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb new file mode 100644 index 0000000000..8747164f32 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb @@ -0,0 +1,7 @@ +chip soc/intel/alderlake + # Disable package C state demotion on Raptorlake as a W/A for S0ix issues + # seen on J0 and Q0 SKUs + register "disable_package_c_state_demotion" = "true" + + device domain 0 on end +end