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mb/google/eve: Work around CLKREQ# timing erratum

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The Sunrise Point-LP PCH built into the Google Pixelbook Eve suffers
from an erratum where the "CLKREQ# asserted to clock active timing" may
exceed the maximum specification, resulting in exit instability from
ASPM L1 state.

This is documented in erratum 47 of the "Intel 100 Series and C230
Series Chipset Family Platform Controller Hub Specification Update"
(Revision 015, December 2018):

https://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf

The Specification Update constrains applicability of the erratum to
Endpoints which do not support LTR or advertise an LTR value of less
than 1 usec.  The reason is that the PCH needs about 1 usec for the
clock to become active after CLKREQ# asserted.  For devices without LTR
support, the maximum is 400 nsec (T_CRLon, PCIe CEM r6.0.1 sec 2.11.2).

The Pixelbook Eve has an Intel 7265 Stone Peak wifi card attached to
Root Port 1.  It seems this wifi card triggers the erratum:  There are
several reports that the wifi card is no longer usable since commit
torvalds/linux@4d4c10f763 ("PCI: Explicitly put devices into D0 when
initializing").

Briefly, coreboot enables all ASPM features on boot, the kernel used to
disable certain ASPM features prior to the commit, now no longer does
and the erratum is thus exposed.  (The commit changed the cached power
state of the wifi card from PCI_UNKNOWN to PCI_D0, which now causes
pcie_config_aspm_link() to no longer disable L1 PCI PM.)

Apply the recommended workaround, which is to disable the associated PCH
CLKREQ# signal to keep the PCIe clock active during L1.

BUG=https://github.com/MrChromebox/firmware/issues/786
TEST=https://bugzilla.kernel.org/show_bug.cgi?id=220705#c31

Change-Id: I00c6555c2b93f46971ea8e4344f8990f86b03a3d
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Lukas Wunner 2026-02-10 17:29:47 +01:00 • committed by Matt DeVillier
commit 71effade58
1 changed files with 3 additions and 1 deletions
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4
src/mainboard/google/eve/devicetree.cb
View file

@ -336,7 +336,9 @@ chip soc/intel/skylake
end end
end # I2C #4 end # I2C #4
device ref pcie_rp1 on device ref pcie_rp1 on
register "PcieRpClkReqSupport[0]" = "true" # Disable CLKREQ# to keep PCIe clock active during L1
# (Erratum 47, Intel 100 Series Chipset Spec Update)
register "PcieRpClkReqSupport[0]" = "false"
register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "true" register "PcieRpLtrEnable[0]" = "true"