support for p4dpe
This commit is contained in:
Ronald G. Minnich
parent
2f828ca0b9
commit
71295c0e4b
7 changed files with 852 additions and 0 deletions
273
src/mainboard/supermicro/p4dpe/Config
Normal file
273
src/mainboard/supermicro/p4dpe/Config
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## Set all of the defaults for an x86 architecture
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##
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arch i386
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript cpu/i386/entry16.lds
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ldscript cpu/i386/entry32.lds
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##
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## Test for logical cpu thats not BSP
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##
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mainboardinit cpu/i786/logical_cpu.inc USE_FALLBACK_IMAGE
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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mainboardinit cpu/i386/reset16.inc USE_FALLBACK_IMAGE
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ldscript cpu/i386/reset16.lds USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset32.inc USE_NORMAL_IMAGE
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ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript arch/i386/lib/id.lds
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##
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## Startup code for secondary CPUS
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##
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mainboardinit arch/i386/smp/secondary.inc
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## This is the early phase of linuxBIOS startup
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## Things are delicate and we test to see if we should
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## failover to another image.
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mainboardinit northbridge/intel/82860/reset_test.inc
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mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE
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mainboardinit southbridge/intel/82801/cmos_failover.inc USE_FALLBACK_IMAGE
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ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup our mtrrs
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##
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mainboardinit cpu/i786/earlymtrr.inc
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##
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## Setup the serial port
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##
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mainboardinit superio/winbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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##
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## Switch temporarily into C code to setup RAM
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##
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#mainboardinit cpu/i786/cache_ram_init.inc
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## mainboardinit cpu/i786/cache_ram_test.inc
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#mainboardinit cpu/i786/cache_ram_start.inc
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#mainboardinit cpu/i786/cache_ram_fini.inc
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#ldscript cpu/i786/cache_ram.lds
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mainboardinit ram/ramtest.inc
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option RAMTEST=1
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mainboardinit ram/dump_northbridge.inc
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##
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## Setup RAM
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##
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#mainboardinit southbridge/intel/82801/smbus.inc
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#mainboardinit sdram/generic_dump_spd.inc
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mainboardinit mainboard/supermicro/p4dpr/mainboard_raminit.inc
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##
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## Include the secondary Configuration files
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##
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northbridge intel/E7500
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southbridge intel/82801ca
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southbridge intel/82870
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nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1
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dir /src/pc80
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dir /src/superio/winbond/w83627hf
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dir /src/ram/
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cpu p5
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cpu p6
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cpu i786
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##
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## Build the objects we have code for in this directory.
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##
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object mainboard.o
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object mtrr_values.o
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object mptable.o HAVE_MP_TABLE
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object irq_tables.o HAVE_PIRQ_TABLE
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###
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### Build options
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###
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##
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## Location of the DIMM EEPROMS on the SMBUS
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## This is fixed into a narrow range by the DIMM package standard.
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##
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option SMBUS_MEM_DEVICE_START=(0xa << 3)
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option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3)
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option SMBUS_MEM_DEVICE_INC=1
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##
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## Customize our winbond superio chip for this motherboard
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##
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option SIO_BASE=0x2e
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option SIO_SYSTEM_CLK_INPUT=SIO_SYSTEM_CLK_INPUT_48MHZ
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##
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## Build code for the fallback boot
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##
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option HAVE_FALLBACK_BOOT=1
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##
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## Build code for using cache as RAM
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##
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option USE_CACHE_RAM=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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option HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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option HAVE_PIRQ_TABLE=1
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##
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## Do not build special code to the keyboard
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##
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option NO_KEYBOARD=1
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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option HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option tabe table
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##
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option HAVE_OPTION_TABLE=1
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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option SMP=1
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option MAX_CPUS=4
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option MAX_PHYSICAL_CPUS=2
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##
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## Build code to setup a generic IOAPIC
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##
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option IOAPIC=1
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##
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## MEMORY_HOLE instructs earlymtrr.inc to
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## enable caching from 0-640KB and to disable
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## caching from 640KB-1MB using fixed MTRRs
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##
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## Enabling this option breaks SMP because secondary
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## CPU identification depends on only variable MTRRs
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## being enabled.
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##
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nooption MEMORY_HOLE
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##
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## Don't do a generic MTRR setup
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## Instead use values from the fixed_mtrr_values array
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##
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option HAVE_MTRR_TABLE=1
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##
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## Enable both fixed and variable MTRRS
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## When we setup MTRRs in mtrr.c
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##
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## We must setup the fixed mtrrs or we confuse SMP secondary
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## processor identification
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##
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option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
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##
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## Figure out which type of linuxBIOS image to build
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## If we aren't a fallback image we must be a normal image
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## This is useful for optional includes
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##
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option USE_FALLBACK_IMAGE=0
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expr USE_NORMAL_IMAGE=!USE_FALLBACK_IMAGE
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###
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### LinuxBIOS layout values
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###
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## ROM_SIZE is the size of boot ROM that this board will use.
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option ROM_SIZE=524288
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE=49152
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00008000
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## For the trick of using cache as ram
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## put the fake ram location at this address
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option CACHE_RAM_BASE=0xfff70000
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option CACHE_RAM_SIZE=0x00010000
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##
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## Use a small 8K stack
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##
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option STACK_SIZE=0x2000
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##
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## Use a small 8K heap
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##
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option HEAP_SIZE=0x2000
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##
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## Clean up the motherboard id strings
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##
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option MAINBOARD_PART_NUMBER=P4DPR
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option MAINBOARD_VENDOR=Supermicro
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##
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## Only use the option table in a normal image
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##
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expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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expr ROM_SECTION_SIZE =(USE_FALLBACK_IMAGE*65536)+(USE_NORMAL_IMAGE*(ROM_SIZE - 65536))
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expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(USE_NORMAL_IMAGE*0)
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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expr PAYLOAD_SIZE =ROM_SECTION_SIZE - ROM_IMAGE_SIZE
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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expr _ROMBASE =ZKERNEL_START + PAYLOAD_SIZE
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##
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## Compute a range of ROM that can cached to speed of linuxBIOS,
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## execution speed.
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##
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expr XIP_ROM_SIZE = 65536
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expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
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104
src/mainboard/supermicro/p4dpe/example-fallback.config
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104
src/mainboard/supermicro/p4dpe/example-fallback.config
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## This will make a target directory of ./fallback
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## This is relative to where the configuration file resides in the filesystem
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target ./fallback
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mainboard supermicro/p4dc6
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## Build a fallback not a normal image.
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option USE_FALLBACK_IMAGE=1
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## Build an image for a 512KB rom
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## ./fallback/romimage is just the last 64KB which we reserve for the fallback image.
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option ROM_SIZE=524288
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#option ROM_SIZE=1048576
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## Select the maximum size the linuxBIOS code can compile to.
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## Allow linuxBIOS to be up to 48KB in size
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option ROM_IMAGE_SIZE=49152
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##
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### The Serial Console
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##
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## Hardware flow control is currently ignored.
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## Enable the Serial Console
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option SERIAL_CONSOLE=1
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## Select the serial console baud rate.
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option TTYS0_BAUD=115200
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#option TTYS0_BAUD=57600
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#option TTYS0_BAUD=38400
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#option TTYS0_BAUD=19200
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#option TTYS0_BAUD=9600
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#option TTYS0_BAUD=4800
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#option TTYS0_BAUD=2400
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#option TTYS0_BAUD=1200
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# Select the serial console base port
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option TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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option TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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option DEFAULT_CONSOLE_LOGLEVEL=9
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## At a maximum only compile in this level of debugging
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option MAXIMUM_CONSOLE_LOGLEVEL=6
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## Use the elf bootloader
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option USE_ELF_BOOT=1
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## Select the boot device
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option USE_GENERIC_ROM=1
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#option BOOT_FLOPPY=1
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#option USE_SERIAL_FILL_INBUF=1
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#option BOOT_IDE=1
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# Load etherboot with the elf bootloader
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# The payload command is relative the build directory
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# So .. is the directory this config file resides in
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payload ../eepro100.ebi
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##
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## Cpu Speed
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##
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option CPU_CLOCK_MULTIPLIER=XEON_X8
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#option CPU_CLOCK_MULTIPLIER=XEON_X9
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#option CPU_CLOCK_MULTIPLIER=XEON_X10
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#option CPU_CLOCK_MULTIPLIER=XEON_X11
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#option CPU_CLOCK_MULTIPLIER=XEON_X12
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#option CPU_CLOCK_MULTIPLIER=XEON_X13
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#option CPU_CLOCK_MULTIPLIER=XEON_X14
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#option CPU_CLOCK_MULTIPLIER=XEON_X15
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#option CPU_CLOCK_MULTIPLIER=XEON_X16
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#option CPU_CLOCK_MULTIPLIER=XEON_X17
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#option CPU_CLOCK_MULTIPLIER=XEON_X18
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#option CPU_CLOCK_MULTIPLIER=XEON_X19
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#option CPU_CLOCK_MULTIPLIER=XEON_X19
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#option CPU_CLOCK_MULTIPLIER=XEON_X20
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#option CPU_CLOCK_MULTIPLIER=XEON_X21
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#option CPU_CLOCK_MULTIPLIER=XEON_X22
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#option CPU_CLOCK_MULTIPLIER=XEON_X23
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##
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## Select power on after power fail setting
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option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
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#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
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105
src/mainboard/supermicro/p4dpe/example-normal.config
Normal file
105
src/mainboard/supermicro/p4dpe/example-normal.config
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## This will make a target directory of ./normal
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## This is relative to where the configuration file resides in the filesystem
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target ./normal
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mainboard supermicro/p4dc6
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## Build a normal not a fallback image.
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option USE_FALLBACK_IMAGE=0
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## Build an image for a 512KB rom
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## ./normal/romimage is the entire rom image except for the last 64KB
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## which are reserved for the fallback image.
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option ROM_SIZE=524288
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#option ROM_SIZE=1048576
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## Select the maximum size the linuxBIOS code can compile to.
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## Allow linuxBIOS to be up to 48KB in size
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option ROM_IMAGE_SIZE=49152
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##
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### The Serial Console
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##
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## Hardware flow control is currently ignored.
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## Enable the Serial Console
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option SERIAL_CONSOLE=1
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## Select the serial console baud rate.
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option TTYS0_BAUD=115200
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#option TTYS0_BAUD=57600
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#option TTYS0_BAUD=38400
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#option TTYS0_BAUD=19200
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#option TTYS0_BAUD=9600
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#option TTYS0_BAUD=4800
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#option TTYS0_BAUD=2400
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#option TTYS0_BAUD=1200
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# Select the serial console base port
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option TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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option TTYS0_LCS=0x3
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##
|
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### Select the linuxBIOS loglevel
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##
|
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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||||
## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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||||
## Request this level of debugging output
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=9
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## At a maximum only compile in this level of debugging
|
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option MAXIMUM_CONSOLE_LOGLEVEL=8
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## Use the elf bootloader
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option USE_ELF_BOOT=1
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## Select the boot device
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option USE_GENERIC_ROM=1
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#option BOOT_FLOPPY=1
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#option USE_SERIAL_FILL_INBUF=1
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#option BOOT_IDE=1
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# Load etherboot with the elf bootloader
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# The payload command is relative the build directory
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# So .. is the directory this config file resides in
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payload ../eepro100.ebi
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||||
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||||
##
|
||||
## Cpu Speed
|
||||
##
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X8
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#option CPU_CLOCK_MULTIPLIER=XEON_X9
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#option CPU_CLOCK_MULTIPLIER=XEON_X10
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#option CPU_CLOCK_MULTIPLIER=XEON_X11
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#option CPU_CLOCK_MULTIPLIER=XEON_X12
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#option CPU_CLOCK_MULTIPLIER=XEON_X13
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#option CPU_CLOCK_MULTIPLIER=XEON_X14
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#option CPU_CLOCK_MULTIPLIER=XEON_X15
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#option CPU_CLOCK_MULTIPLIER=XEON_X16
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option CPU_CLOCK_MULTIPLIER=XEON_X17
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#option CPU_CLOCK_MULTIPLIER=XEON_X18
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#option CPU_CLOCK_MULTIPLIER=XEON_X19
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#option CPU_CLOCK_MULTIPLIER=XEON_X19
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#option CPU_CLOCK_MULTIPLIER=XEON_X20
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#option CPU_CLOCK_MULTIPLIER=XEON_X21
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||||
#option CPU_CLOCK_MULTIPLIER=XEON_X22
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||||
#option CPU_CLOCK_MULTIPLIER=XEON_X23
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||||
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||||
##
|
||||
## Select power on after power fail setting
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||||
option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
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#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
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||||
43
src/mainboard/supermicro/p4dpe/irq_tables.c
Normal file
43
src/mainboard/supermicro/p4dpe/irq_tables.c
Normal file
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@ -0,0 +1,43 @@
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/* PCI: Interrupt Routing Table found at 0x4011ce40 size = 416 */
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||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
0x52495024, /* u32 signature */
|
||||
0x0100, /* u16 version */
|
||||
416, /* u16 Table size 32+(16*devices) */
|
||||
0x00, /* u8 Bus 0 */
|
||||
0xf8, /* u8 Device 1, Function 0 */
|
||||
0x0000, /* u16 reserve IRQ for PCI */
|
||||
0x8086, /* u16 Vendor */
|
||||
0x122e, /* Device ID */
|
||||
0x00000000, /* u32 miniport_data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x94, /* u8 checksum - mod 256 checksum must give zero */
|
||||
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, 0x00, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x00, 0x10, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x01, 0xe8, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x02, 0x08, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x01, 0x00},
|
||||
{0x02, 0x18, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x0a, 0x00},
|
||||
{0x02, 0x10, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x03, 0x00},
|
||||
{0x01, 0xf8, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x03, 0x08, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x02, 0x00},
|
||||
{0x03, 0x10, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x05, 0x00},
|
||||
{0x03, 0x18, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x06, 0x00},
|
||||
{0x03, 0x20, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x0b, 0x00},
|
||||
{0x00, 0x20, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x10, 0xe8, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x11, 0x08, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}}, 0x03, 0x00},
|
||||
{0x10, 0xf8, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x12, 0x08, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}}, 0x04, 0x00},
|
||||
{0x00, 0xf0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x04, 0x08, {{0x60, 0xdcb8}, {0x60, 0xdcb8}, {0x60, 0xdcb8}, {0x60, 0xdcb8}}, 0x07, 0x00},
|
||||
{0x04, 0x10, {{0x61, 0xdcb8}, {0x61, 0xdcb8}, {0x61, 0xdcb8}, {0x61, 0xdcb8}}, 0x08, 0x00},
|
||||
{0x04, 0x18, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x09, 0x00},
|
||||
{0x00, 0xe8, {{0x60, 0xdcb8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x00, 0xe9, {{0x00, 0xdef8}, {0x63, 0xdcb8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x00, 0xea, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x62, 0xdcb8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x00, 0xf8, {{0x62, 0xdcb8}, {0x61, 0xdcb8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}
|
||||
}
|
||||
};
|
||||
209
src/mainboard/supermicro/p4dpe/mainboard.c
Normal file
209
src/mainboard/supermicro/p4dpe/mainboard.c
Normal file
|
|
@ -0,0 +1,209 @@
|
|||
#include <arch/io.h>
|
||||
#include <part/mainboard.h>
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <southbridge/intel/82801.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <pc80/isa_dma.h>
|
||||
#include <cpu/i786/multiplier.h>
|
||||
#include <cpu/i786/thermal_monitoring.h>
|
||||
#include <cpu/p6/msr.h>
|
||||
#include <superio/w83627hf.h>
|
||||
#include <superio/generic.h>
|
||||
#include <subr.h>
|
||||
#include <smbus.h>
|
||||
#include <ramtest.h>
|
||||
#include <northbridge/intel/82860/rdram.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
|
||||
#define SMBUS_MEM_DEVICE_0 (0xa << 3)
|
||||
extern int rdram_chips; /* number of ram chips on the rimms */
|
||||
|
||||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
{
|
||||
0, 6, 1, 7
|
||||
};
|
||||
|
||||
#ifndef CPU_CLOCK_MULTIPLIER
|
||||
#define CPU_CLOCK_MULTIPLIER XEON_X17
|
||||
#endif
|
||||
|
||||
#define MAINBOARD_POWER_ON 1
|
||||
#define MAINBOARD_POWER_OFF 2
|
||||
|
||||
#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
||||
#endif
|
||||
|
||||
static void set_power_on_after_power_fail(int setting)
|
||||
{
|
||||
switch(setting) {
|
||||
case MAINBOARD_POWER_ON:
|
||||
default:
|
||||
ich3_power_after_power_fail(1);
|
||||
w832627hf_power_after_power_fail(POWER_ON);
|
||||
break;
|
||||
case MAINBOARD_POWER_OFF:
|
||||
ich3_power_after_power_fail(0);
|
||||
w832627hf_power_after_power_fail(POWER_OFF);
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void set_thermal_monitoring(int thermal_monitoring)
|
||||
{
|
||||
int tm_high,tm_low;
|
||||
|
||||
rdmsr(MISC_ENABLE,tm_low,tm_high);
|
||||
if(thermal_monitoring != THERMAL_MONITORING_OFF) {
|
||||
tm_low |= THERMAL_MONITORING_SET;
|
||||
}
|
||||
else {
|
||||
tm_low &= ~THERMAL_MONITORING_SET;
|
||||
}
|
||||
wrmsr(MISC_ENABLE,tm_low,tm_high);
|
||||
return;
|
||||
}
|
||||
|
||||
void mainboard_fixup(void)
|
||||
{
|
||||
int cpu_clock_multiplier;
|
||||
int power_on_after_power_fail;
|
||||
int thermal_monitoring;
|
||||
ich3_enable_ioapic();
|
||||
p64h2_enable_ioapic();
|
||||
ich3_enable_serial_irqs();
|
||||
ich3_enable_ide(1,1);
|
||||
ich3_rtc_init();
|
||||
ich3_lpc_route_dma(0xff);
|
||||
isa_dma_init();
|
||||
ich3_1e0_misc();
|
||||
ich3_1f0_misc();
|
||||
|
||||
cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER;
|
||||
if(get_option(&cpu_clock_multiplier, "CPU_clock_speed"))
|
||||
cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER;
|
||||
ich3_set_cpu_multiplier(cpu_clock_multiplier);
|
||||
|
||||
power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
if(get_option(&power_on_after_power_fail, "power_on_after_power_fail"))
|
||||
power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
set_power_on_after_power_fail(power_on_after_power_fail);
|
||||
|
||||
thermal_monitoring = THERMAL_MONITORING_OFF;
|
||||
if(get_option(&thermal_monitoring, "thermal_monitoring"))
|
||||
thermal_monitoring = THERMAL_MONITORING_OFF;
|
||||
set_thermal_monitoring(thermal_monitoring);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
ich3_hard_reset();
|
||||
}
|
||||
|
||||
static void select_rdram_i2c(void)
|
||||
{
|
||||
unsigned char byte;
|
||||
w83627hf_enter_pnp(SIO_BASE);
|
||||
byte = pnp_read_config(SIO_BASE, 0x2b);
|
||||
byte |= 0x30;
|
||||
pnp_write_config(SIO_BASE, byte, 0x2b);
|
||||
pnp_set_logical_device(SIO_BASE, GPIO_PORT2_DEVICE);
|
||||
pnp_set_enable(SIO_BASE, 1);
|
||||
byte = pnp_read_config(SIO_BASE, 0xf0);
|
||||
byte &= ~(1 << 3);
|
||||
pnp_write_config(SIO_BASE, byte, 0xf0);
|
||||
w83627hf_exit_pnp(SIO_BASE);
|
||||
}
|
||||
|
||||
#if 0
|
||||
void cache_ram_start(void)
|
||||
{
|
||||
int error;
|
||||
|
||||
error = 0;
|
||||
/* displayinit MUST PRECEDE ALL PRINTK! */
|
||||
|
||||
#if 1
|
||||
displayinit();
|
||||
#endif
|
||||
printk_info("Finding PCI configuration type.\n");
|
||||
pci_set_method();
|
||||
printk_info("Setting up smbus controller\n");
|
||||
smbus_setup();
|
||||
ich3_rtc_init();
|
||||
printk_info("Selecting rdram i2c bus\n");
|
||||
select_rdram_i2c();
|
||||
|
||||
#if 0
|
||||
display_smbus_spd();
|
||||
#endif
|
||||
|
||||
init_memory();
|
||||
|
||||
#if 0
|
||||
{
|
||||
unsigned long addr;
|
||||
for(addr = 0; addr < 0x20000000; addr += 0x02000000) {
|
||||
ram_fill(addr, addr + 0x400);
|
||||
}
|
||||
/* Do some dummy writes to flush a write cache, in the
|
||||
* processor.
|
||||
*/
|
||||
ram_fill(0xc0000000, 0xc0000400);
|
||||
for(addr = 0; addr < 0x20000000; addr += 0x02000000) {
|
||||
ram_verify(addr, addr + 0x400, 1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if 1
|
||||
printk_debug("starting ramcheck\n");
|
||||
error |= ramcheck(0x00000000, 0x00080000, 40);
|
||||
error |= ramcheck(0x02000000, 0x02080000, 40);
|
||||
error |= ramcheck(0x04000000, 0x04080000, 40);
|
||||
error |= ramcheck(0x06000000, 0x06080000, 40);
|
||||
error |= ramcheck(0x08000000, 0x08080000, 40);
|
||||
error |= ramcheck(0x0a000000, 0x0a080000, 40);
|
||||
error |= ramcheck(0x0c000000, 0x0c080000, 40);
|
||||
error |= ramcheck(0x0e000000, 0x0e080000, 40);
|
||||
error |= ramcheck(0x1a000000, 0x1a080000, 40);
|
||||
#if 0
|
||||
error |= ramcheck(0x10000000, 0x10080000, 20);
|
||||
error |= ramcheck(0x12000000, 0x12080000, 20);
|
||||
error |= ramcheck(0x14000000, 0x14080000, 20);
|
||||
error |= ramcheck(0x16000000, 0x16080000, 20);
|
||||
error |= ramcheck(0x18000000, 0x18080000, 20);
|
||||
error |= ramcheck(0x1a000000, 0x1a080000, 20);
|
||||
error |= ramcheck(0x1c000000, 0x1c080000, 20);
|
||||
error |= ramcheck(0x1e000000, 0x1e080000, 20);
|
||||
#endif
|
||||
#endif
|
||||
#if 0
|
||||
error |= ramcheck(0x00000000, 0x00080000, 20);
|
||||
#endif
|
||||
#if 0
|
||||
display_rdram_regs(rdram_chips );
|
||||
#endif
|
||||
#if 0
|
||||
display_mch_regs();
|
||||
#endif
|
||||
if (error) {
|
||||
printk_err("Something isn't working!!!\n");
|
||||
while(1);
|
||||
} else {
|
||||
printk_info("Leaving cacheram...\n");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
1
src/mainboard/supermicro/p4dpe/mainboard_raminit.inc
Normal file
1
src/mainboard/supermicro/p4dpe/mainboard_raminit.inc
Normal file
|
|
@ -0,0 +1 @@
|
|||
|
||||
117
src/mainboard/supermicro/p4dpe/mptable.c
Normal file
117
src/mainboard/supermicro/p4dpe/mptable.c
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
/* generatred by MPTable, version 2.0.15*/
|
||||
/* as modified by RGM for LinuxBIOS */
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <string.h>
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "LNXI ";
|
||||
static const char productid[12] = "P4DPE ";
|
||||
struct mp_config_table *mc;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc, processor_map);
|
||||
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
smp_write_bus(mc, 0, "PCI ");
|
||||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "PCI ");
|
||||
smp_write_bus(mc, 4, "PCI ");
|
||||
smp_write_bus(mc, 5, "PCI ");
|
||||
smp_write_bus(mc, 6, "PCI ");
|
||||
smp_write_bus(mc, 7, "PCI ");
|
||||
smp_write_bus(mc, 8, "ISA ");
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
dev = pci_find_slot(1, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 3, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(1, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 4, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(4, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 5, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(4, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 8, 0x20, base);
|
||||
}
|
||||
}
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x3, 0x2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x4, 0x2, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x5, 0x2, 0x5);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x6, 0x2, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x7, 0x2, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x8, 0x2, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x9, 0x2, 0x9);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xc, 0x2, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xf, 0x2, 0xf);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x8, 0x3, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x9, 0x3, 0x5);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x7, 0x4, 0x2, 0x10);
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p
|
||||
",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue