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remmove mst_t from include and southbridge.

Browse source 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@396 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2007-06-28 17:00:36 +00:00
commit 7044158043
3 changed files with 18 additions and 19 deletions
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11
include/arch/x86/msr.h
View file

@ -21,16 +21,15 @@
#define CPU_X86_MSR_H
/* standard MSR operations, everyone has written these one hundred times */
typedef struct msr_struct
struct msr
{
unsigned lo;
unsigned hi;
} msr_t;
};
static inline msr_t rdmsr(unsigned index)
static inline struct msr rdmsr(unsigned index)
{
msr_t result;
struct msr result;
__asm__ __volatile__ (
"rdmsr"
: "=a" (result.lo), "=d" (result.hi)
@ -39,7 +38,7 @@ static inline msr_t rdmsr(unsigned index)
return result;
}
static inline void wrmsr(unsigned index, msr_t msr)
static inline void wrmsr(unsigned index, struct msr msr)
{
__asm__ __volatile__ (
"wrmsr"

12
southbridge/amd/cs5536/cs5536.c
View file

@ -36,7 +36,7 @@ extern void setup_i8259(void);
struct msrinit {
u32 msrnum;
msr_t msr;
struct msr msr;
};
/* Master Configuration Register for Bus Masters.*/
@ -144,7 +144,7 @@ static void pm_chipset_init(void)
*/
static void chipset_flash_setup(void)
{
msr_t msr;
struct msr msr;
int i;
int numEnabled = 0;
@ -207,7 +207,7 @@ static void enable_ide_nand_flash_header(void)
*/
static void lpc_init(struct southbridge_amd_cs5536_config *sb)
{
msr_t msr;
struct msr msr;
if (sb->lpc_serirq_enable) {
msr.lo = sb->lpc_serirq_enable;
@ -253,7 +253,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb)
*/
static void uarts_init(struct southbridge_amd_cs5536_config *sb)
{
msr_t msr;
struct msr msr;
u16 addr = 0;
u32 gpio_addr;
struct device *dev;
@ -417,7 +417,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
{
u32 *bar;
msr_t msr;
struct msr msr;
struct device *dev;
dev = dev_find_device(PCI_VENDOR_ID_AMD,
@ -511,7 +511,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
void chipsetinit(void)
{
struct device *dev;
msr_t msr;
struct msr msr;
u32 msrnum;
struct southbridge_amd_cs5536_config *sb;
struct msrinit *csi;

14
southbridge/amd/cs5536/cs5536_early_setup.c
View file

@ -41,7 +41,7 @@
*/
void cs5536_setup_extmsr(void)
{
msr_t msr;
struct msr msr;
/* Forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM. */
msr.hi = msr.lo = 0x00000000;
@ -74,7 +74,7 @@ void cs5536_setup_idsel(void)
*/
void cs5536_usb_swapsif(void)
{
msr_t msr;
struct msr msr;
msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5);
@ -97,7 +97,7 @@ void cs5536_usb_swapsif(void)
*/
void cs5536_setup_iobase(void)
{
msr_t msr;
struct msr msr;
/* Setup LBAR for SMBus controller. */
msr.hi = 0x0000f001;
@ -174,7 +174,7 @@ void cs5536_setup_smbus_gpio(void)
*/
void cs5536_disable_internal_uart(void)
{
msr_t msr;
struct msr msr;
/* The UARTs default to enabled.
* Disable and reset them and configure them later (SIO init).
@ -201,7 +201,7 @@ void cs5536_disable_internal_uart(void)
*/
void cs5536_setup_cis_mode(void)
{
msr_t msr;
struct msr msr;
/* Setup CPU interface serial to mode B to match CPU. */
msr = rdmsr(GLPCI_SB_CTRL);
@ -217,7 +217,7 @@ void cs5536_setup_cis_mode(void)
*/
void cs5536_setup_onchipuart(void)
{
msr_t msr;
struct msr msr;
/* Setup early for polling only mode.
* 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1.
@ -276,7 +276,7 @@ void cs5536_setup_onchipuart(void)
*/
void cs5536_early_setup(void)
{
msr_t msr;
struct msr msr;
/* Note: you can't do prints in here in most cases, and we don't want
* to hang on serial, so they are commented out.