From 70253f3293ee1b4c35c9e5b31c47f4e46286e66c Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Fri, 8 Feb 2002 00:59:00 +0000 Subject: [PATCH] PIRQ for CUA --- src/mainboard/asus/cua/irq_tables.c | 50 +++++++++++++++-------------- 1 file changed, 26 insertions(+), 24 deletions(-) diff --git a/src/mainboard/asus/cua/irq_tables.c b/src/mainboard/asus/cua/irq_tables.c index febb23fd64..a7ec10e343 100644 --- a/src/mainboard/asus/cua/irq_tables.c +++ b/src/mainboard/asus/cua/irq_tables.c @@ -1,31 +1,33 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + #include -/* NOTE -- THIS IS A PLACEHOLDER -- WE NEED TO FIX THIS */ -#define CHECKSUM 0xe6 const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*5, /* there can be total 5 devices on the bus */ - 0x00, /* Bus 0 */ - 0x08, /* Device 1, Function 0 */ - 0x0A20, /* reserve IRQ 11, 9, 5, for PCI */ - 0x1039, /* Silicon Integrated System */ - 0x0008, /* SiS 85C503/5513 ISA Bridge */ - 0x00, /* u8 miniport_data - "crap" */ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*9, /* there can be total 9 devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0x38, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x10b9, /* Vendor */ + 0x1533, /* Device */ + 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */ + 0x33, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, 0x58, {{0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}}, - 0x01, 0x00}, - {0x00, 0x60, {{0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}}, - 0x02, 0x00}, - {0x00, 0x01, {{0x61, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, - 0x00, 0x00}, - {0x00, 0x10, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}}, - 0x00, 0x00}, - {0x00, 0x0a, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}}, - 0x00, 0x00}, + {0,0x60, {{0x1, 0x1eb8}, {0x2, 0x1eb8}, {0x3, 0x1eb8}, {0x4, 0x1eb8}}, 0x1, 0}, + {0,0x58, {{0x2, 0x1eb8}, {0x3, 0x1eb8}, {0x4, 0x1eb8}, {0x1, 0x1eb8}}, 0x2, 0}, + {0,0x50, {{0x3, 0x1eb8}, {0x4, 0x1eb8}, {0x1, 0x1eb8}, {0x2, 0x1eb8}}, 0x3, 0}, + {0,0x48, {{0x4, 0x1eb8}, {0x1, 0x1eb8}, {0x2, 0x1eb8}, {0x3, 0x1eb8}}, 0x4, 0}, + {0,0x68, {{0x4, 0x1eb8}, {0x1, 0x1eb8}, {0x2, 0x1eb8}, {0x3, 0x1eb8}}, 0x5, 0}, + {0,0x70, {{0x3, 0x1eb8}, {0x4, 0x1eb8}, {0x1, 0x1eb8}, {0x2, 0x1eb8}}, 0x6, 0}, + {0,0x30, {{0x8, 0x1eb8}, {0, 0x1eb8}, {0, 0x1eb8}, {0, 0x1eb8}}, 0, 0}, + {0,0xa0, {{0x59, 0x1eb8}, {0, 0x1eb8}, {0, 0x1eb8}, {0, 0x1eb8}}, 0, 0}, + {0x1,0, {{0x1, 0x1eb8}, {0, 0x1eb8}, {0, 0x1eb8}, {0, 0x1eb8}}, 0, 0}, } }; -