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rockchip: configure lpddr odt properly

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The wrong offsets were being used for the GRF_SOC_CON2 register. This also
configures odt based on the value of odt in the sdram_params for lpddr systems.

BUG=chrome-os-partner:37346
TEST=boot veyron_speedy and veyron_jerry
BRANCH=None

Change-Id: Ic0c18cc7ccf861ef8749e6c950fab9a2802e5f26
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/255584
Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 403ab13de17290dc3766bd6f1a03b6effbe58b41)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/255975
This commit is contained in:
Derek Basehore 2015-03-03 12:30:43 -08:00 • committed by ChromeOS Commit Bot
commit 701167a33e
1 changed files with 4 additions and 4 deletions
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8
src/soc/rockchip/rk3288/sdram.c
View file

@ -456,11 +456,11 @@ static struct rk3288_msch_regs * const rk3288_msch[2] = {
| ((1 << (3 + (ch))) << 16))
/* GRF_SOC_CON2 */
#define PUBL_LPDDR3_EN(ch, n) RK_CLRSETBITS(1 << (10 + (3 * (ch))), \
#define PCTL_LPDDR3_ODT_EN(ch, n) RK_CLRSETBITS(1 << (10 + (3 * (ch))), \
(n) << (10 + (3 * (ch))))
#define PCTL_LPDDR3_ODT_EN(ch, n) RK_CLRSETBITS(1 << (9 + (3 * (ch))), \
#define PCTL_BST_DISABLE(ch, n) RK_CLRSETBITS(1 << (9 + (3 * (ch))), \
(n) << (9 + (3 * (ch))))
#define PCTL_BST_DISABLE(ch, n) RK_CLRSETBITS(1 << (8 + (3 * (ch))), \
#define PUBL_LPDDR3_EN(ch, n) RK_CLRSETBITS(1 << (8 + (3 * (ch))), \
(n) << (8 + (3 * (ch))))
/* mr1 for ddr3 */
@ -616,7 +616,7 @@ static void pctl_cfg(u32 channel,
writel(PUBL_LPDDR3_EN(channel, 1)
| PCTL_BST_DISABLE(channel, 1)
| PCTL_LPDDR3_ODT_EN(channel, 1),
| PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt),
&rk3288_grf->soc_con2);
break;