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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/totalimpact/briq/Config.lb

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+##
+## Config file for the Total Impact briQ
+##
+
+uses PCIC0_CFGADDR 
+uses PCIC0_CFGDATA 
+uses UART0_IO_BASE
+uses CONFIG_BRIQ_750FX
+uses CONFIG_BRIQ_7400
+
+##
+## Set PCI registers
+##
+default PCIC0_CFGADDR=0xeec00000
+default PCIC0_CFGDATA=0xeec00004
+
+##
+## Set UART base address
+##
+default UART0_IO_BASE=0xef600300
+
+##
+## Early board initialization, called from ppc_main()
+##
+initobject init.c
+driver pci_bridge.c
+
+arch ppc end
+
+if CONFIG_BRIQ_750FX
+	cpu ppc/ppc7xx end
+end
+if CONFIG_BRIQ_7400
+	cpu ppc/mpc74xx end
+end
+
+##
+## Include the secondary Configuration files 
+##
+southbridge winbond/w83c553 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"

src/mainboard/totalimpact/briq/init.c

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+/*
+ * Copyright (C) 2003, Greg Watson <gwatson@lanl.gov>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Do very early board initialization:
+ *
+ * - Configure External Bus (EBC)
+ * - Setup Flash
+ * - Setup NVRTC
+ * - Setup Board Control and Status Registers (BCSR)
+ * - Enable UART0 for debugging
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc.h>
+#include <ppc4xx.h>
+#include <arch/io.h>
+#include <timer.h>
+
+void
+board_init(void)
+{
+	/*
+	 * Configure FLASH
+	 */
+	mtebc(pb0cr, 0xFC0DC000);
+	mtebc(pb0ap, 0x02000000);
+
+	/*
+	 * Configure NVTRC/BCSR
+	 */
+	mtebc(pb4cr, 0xF4058000);
+	mtebc(pb4ap, 0x04050000);
+	
+	/*
+	 * Enable PCI
+	 */
+	outb(0x80, 0xF4000001);
+
+	/*
+	 * Enable UART0
+	 */
+	outb(0x20, 0xF4000003);
+
+	/*
+	 * Cycle LEDs to show something is happening...
+	 */
+	outb(0x07, 0xF4000009);
+	udelay(100000);
+	outb(0x0B, 0xF4000009);
+	udelay(100000);
+	outb(0x0D, 0xF4000009);
+	udelay(100000);
+	outb(0x0E, 0xF4000009);
+}