From 6fce823512f5db5a09a9c89048334c3524c69a24 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 6 Mar 2014 10:56:16 -0600 Subject: [PATCH] baytrail: stop e820 reserving default SMM region The default SMM region was previously being reserved. Stop doing that in order to not antagonize certain kernel loaders and payloads when there are low e820 ram reservations. Since the default SMM region is not marked as reserved the region needs backed up and restored on resume. BUG=chrome-os-partner:26563 BRANCH=baytrail TEST=Built and booted. Suspended and resumed. Confirmed no more e820 reservations at default SMM region. Also noted resume times are still at ~200ms. Change-Id: Icf21d40a790b0c1b0b8c2111f779abb996adce56 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/189084 --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/cpu.c | 4 ++++ src/soc/intel/baytrail/northcluster.c | 10 ++-------- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 66f0baf8d0..c54d6ec423 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,6 +9,7 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select ALT_CBFS_LOAD_PAYLOAD + select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CACHE_ROM diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 65fd3c2b5e..fb2e1c0b75 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -105,6 +105,7 @@ void baytrail_init_cpus(device_t dev) const struct pattrs *pattrs = pattrs_get(); struct mp_params mp_params; uint32_t bsmrwac; + void *default_smm_area; /* Set up MTRRs based on physical address size. */ x86_setup_fixed_mtrrs(); @@ -118,6 +119,7 @@ void baytrail_init_cpus(device_t dev) mp_params.num_records = ARRAY_SIZE(mp_steps); mp_params.microcode_pointer = pattrs->microcode_patch; + default_smm_area = backup_default_smm_area(); /* * Configure the BUNIT to allow dirty cache line evictions in non-SMM @@ -136,6 +138,8 @@ void baytrail_init_cpus(device_t dev) if (mp_init(cpu_bus, &mp_params)) { printk(BIOS_ERR, "MP initialization failure.\n"); } + + restore_default_smm_area(default_smm_area); } static void baytrail_core_init(device_t cpu) diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index ff5734cd55..6052477745 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -89,14 +89,8 @@ static void nc_read_resources(device_t dev) mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); - /* 0 -> SMM_DEFAULT_BASE cacheable ram. */ - ram_resource(dev, index++, 0, RES_IN_KiB(SMM_DEFAULT_BASE)); - /* Default SMM region is cacheable but reserved for coreboot */ - reserved_ram_resource(dev, index++, RES_IN_KiB(SMM_DEFAULT_BASE), - RES_IN_KiB(SMM_DEFAULT_SIZE)); - - /* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE - > 0xa0000 */ - base_k = RES_IN_KiB(SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE); + /* 0 -> 0xa0000 */ + base_k = RES_IN_KiB(0); size_k = RES_IN_KiB(0xa0000) - base_k; ram_resource(dev, index++, base_k, size_k);