diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 591abbeaae..f4785bb365 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -36,6 +36,21 @@ enum chip_pl2_4_cfg {
 	value_not_set /* vr_config internal use only */
 };
 
+/* Gfx related */
+enum igd_dvmt50_pre_alloc {
+	IGD_SM_0MB = 0x00,
+	IGD_SM_32MB = 0x01,
+	IGD_SM_64MB = 0x02,
+	IGD_SM_96MB = 0x03,
+	IGD_SM_128MB = 0x04,
+};
+
+enum igd_aperture_size {
+	IGD_AP_SZ_128MB = 0x00,
+	IGD_AP_SZ_256MB = 0x01,
+	IGD_AP_SZ_512MB = 0x02,
+};
+
 struct soc_intel_cannonlake_config {
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
diff --git a/src/soc/intel/cannonlake/include/soc/cfr.h b/src/soc/intel/cannonlake/include/soc/cfr.h
index ae61799a68..1526256703 100644
--- a/src/soc/intel/cannonlake/include/soc/cfr.h
+++ b/src/soc/intel/cannonlake/include/soc/cfr.h
@@ -8,6 +8,7 @@
 #define CANNONLAKE_CFR_H
 
 #include <drivers/option/cfr_frontend.h>
+#include <soc/soc_chip.h>
 
 /* FSP hyperthreading */
 static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
@@ -26,11 +27,11 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 	.opt_name	= "igd_aperture_size",
 	.ui_name	= "IGD Aperture Size",
 	.ui_helptext	= "Select the Aperture Size",
-	.default_value	= 1,
+	.default_value	= IGD_AP_SZ_256MB,
 	.values		= (const struct sm_enum_value[]) {
-				{ "128 MB",		0	},
-				{ "256 MB",		1	},
-				{ "512 MB",		2	},
+				{ "128 MB",	IGD_AP_SZ_128MB	},
+				{ "256 MB",	IGD_AP_SZ_256MB	},
+				{ "512 MB",	IGD_AP_SZ_512MB	},
 				SM_ENUM_VALUE_END		},
 });
 
@@ -39,12 +40,12 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 	.opt_name	= "igd_dvmt_prealloc",
 	.ui_name	= "IGD DVMT Size",
 	.ui_helptext	= "Size of memory preallocated for internal graphics",
-	.default_value	= 2,
+	.default_value	= IGD_SM_64MB,
 	.values		= (const struct sm_enum_value[]) {
-				{ "32 MB",		1	},
-				{ "64 MB",		2	},
-				{ "96 MB",		3	},
-				{ "128 MB",		4	},
+				{ "32 MB",	IGD_SM_32MB	},
+				{ "64 MB",	IGD_SM_64MB	},
+				{ "96 MB",	IGD_SM_96MB	},
+				{ "128 MB",	IGD_SM_128MB	},
 				SM_ENUM_VALUE_END		},
 });
 
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 74812f31bf..a8523f14ab 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -14,6 +14,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>
 #include <soc/romstage.h>
+#include <soc/soc_chip.h>
 #include <types.h>
 
 #include "../chip.h"
@@ -37,8 +38,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
 		/* Set IGD stolen size to 64MB. */
 		m_cfg->InternalGfx = 1;
-		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", 2);
-		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", 1);
+		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_64MB);
+		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
 	} else {
 		m_cfg->InternalGfx = 0;
 		m_cfg->IgdDvmt50PreAlloc = 0;