Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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84 changed files with 5865 additions and 387 deletions
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@ -31,7 +31,7 @@
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#define TOP_MEM_MASK 0x007fffff
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#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
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#ifndef __ROMCC__
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#if !defined( __ROMCC__ ) && !defined (ASSEMBLY)
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void amd_setup_mtrrs(void);
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#endif /* __ROMCC__ */
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@ -4,9 +4,14 @@
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static void report_bist_failure(unsigned long bist)
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{
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if (bist != 0) {
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#if CONFIG_USE_INIT
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printk_emerg("BIST failed: %08x", bist);
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#else
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print_emerg("BIST failed: ");
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print_emerg_hex32(bist);
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#endif
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die("\r\n");
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}
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}
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@ -41,7 +41,7 @@ static inline void disable_cache(void)
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wbinvd();
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}
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#ifndef __ROMCC__
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#if !defined( __ROMCC__) && defined (__GNUC__)
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void x86_enable_cache(void);
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#endif /* !__ROMCC__ */
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@ -1,8 +1,7 @@
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#ifndef CPU_X86_MSR_H
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#define CPU_X86_MSR_H
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#ifdef __ROMCC__
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#if defined( __ROMCC__) && !defined (__GNUC__)
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typedef __builtin_msr_t msr_t;
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@ -16,9 +15,7 @@ static void wrmsr(unsigned long index, msr_t msr)
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__builtin_wrmsr(index, msr.lo, msr.hi);
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}
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#endif /* __ROMCC__ */
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#if defined(__GNUC__) && !defined(__ROMCC__)
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#else
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typedef struct msr_struct
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{
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@ -46,7 +43,7 @@ static inline void wrmsr(unsigned index, msr_t msr)
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);
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}
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#endif /* __GNUC__ */
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#endif /* ROMCC__ && !__GNUC__ */
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#endif /* CPU_X86_MSR_H */
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@ -32,7 +32,7 @@
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#define MTRRfix4K_F8000_MSR 0x26f
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#if !defined(__ROMCC__) && !defined(ASSEMBLY)
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#if !defined(__ROMCC__) && !defined (ASSEMBLY)
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void x86_setup_mtrrs(void);
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int x86_mtrr_check(void);
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@ -1,6 +1,6 @@
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#ifndef DELAY_H
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#define DELAY_H
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#ifndef __ROMCC__
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#if !defined( __ROMCC__) && defined (__GNUC__)
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void udelay(unsigned usecs);
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void mdelay(unsigned msecs);
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