From 6c5a4f9b5f5ceec6cd3bc1ade8d243c2e9a10a14 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Mon, 8 Jul 2013 18:41:02 +0800 Subject: [PATCH] exynos5250: Correct DDR3 Phy-reset value names. The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real phy-reset is a low-active pin, so "off(0)" will trigger "start to reset". To prevent confusion, we should rename the constants to "RESET_ENABLE" and "RESET_DISABLE". BUG=none TEST=emerge-daisy chromeos-coreboot-snow BRANCH=none Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9 Reviewed-on: https://gerrit.chromium.org/gerrit/61081 Tested-by: Hung-Te Lin Reviewed-by: David Hendricks Commit-Queue: Hung-Te Lin --- src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 4 ++-- src/cpu/samsung/exynos5250/setup.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index cb5c61389f..11940d1ba5 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -33,8 +33,8 @@ static void reset_phy_ctrl(void) { struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl); - writel(LPDDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); + writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &clk->lpddr3phy_ctrl); + writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &clk->lpddr3phy_ctrl); #if 0 /* diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index 942a3f1ab5..1f77b2e267 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -624,8 +624,8 @@ struct exynos5_phy_control; */ #define DECPROTXSET 0xFF -#define LPDDR3PHY_CTRL_PHY_RESET (1 << 0) -#define LPDDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) +#define LPDDR3PHY_CTRL_PHY_RESET_DISABLE (1 << 0) +#define LPDDR3PHY_CTRL_PHY_RESET_ENABLE (0 << 0 ) #define PHY_CON0_RESET_VAL 0x17020a40 #define P0_CMD_EN (1 << 14)