From 6b61e4ce687f96a19183d8e2bafc7fd1a09ceb84 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 8 Jan 2026 16:46:56 +0100 Subject: [PATCH] soc/amd/glinda: Fill in fch_rt_device_enable_map Currently FSP modifies the AOAC bits of the FCH devices and thus needs the current status passed via fch_rt_device_enable_map. By default fch_rt_device_enable_map is 0, effectly disabling all FCH devices, including the debug UART. This causes a hang at boot. Fill fch_rt_device_enable_map in SoC code. TEST=Can boot on amd/birman_plus again. Change-Id: I00ef35ea6fe11939c4154940fef8cb902955fe27 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/91160 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/glinda/fsp_m_params.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c index 32a708fd70..ff5f04c7f2 100644 --- a/src/soc/amd/glinda/fsp_m_params.c +++ b/src/soc/amd/glinda/fsp_m_params.c @@ -3,6 +3,7 @@ /* TODO: Update for Glinda */ /* TODO: See what can be moved to common */ +#include #include #include #include @@ -13,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -176,6 +178,31 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->usb_phy_ptr = 0; } + /* Sync AOAC devices */ + int fch_aoac_devs[] = { + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, + FCH_AOAC_DEV_UART0, + FCH_AOAC_DEV_UART1, + FCH_AOAC_DEV_UART2, + FCH_AOAC_DEV_UART3, + FCH_AOAC_DEV_UART4, + FCH_AOAC_DEV_I3C0, + FCH_AOAC_DEV_I3C1, + FCH_AOAC_DEV_I3C2, + FCH_AOAC_DEV_I3C3, + }; + + for (int i = 0; i < ARRAY_SIZE(fch_aoac_devs); i++) { + const int mask = BIT(fch_aoac_devs[i]); + if (is_aoac_device_enabled(fch_aoac_devs[i])) + mcfg->fch_rt_device_enable_map |= mask; + else + mcfg->fch_rt_device_enable_map &= ~mask; + } + fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); mb_pre_fspm(mcfg);