From 6b5a872ce850b92a79445e27eee3c4eabe76a30d Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Wed, 10 Dec 2025 17:18:56 +0800 Subject: [PATCH] soc/mediatek: Pass dsi_regs/mipi_tx_regs to DSI API In preparation for the upcoming DSI dual channel support, pass dsi_regs and mipi_tx_regs to DSI functions that need to access these registers. BUG=b:424782827 TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a BRANCH=none Change-Id: Ia0c9051148e38a7703119f800d417f2f8b52f78a Signed-off-by: Payne Lin Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/90446 Reviewed-by: Yidi Lin Reviewed-by: Chen-Tsung Hsieh Tested-by: build bot (Jenkins) --- src/soc/mediatek/common/dsi_common.c | 6 +-- src/soc/mediatek/common/dsi_v1.c | 46 ++++++++++--------- .../mediatek/common/include/soc/dsi_common.h | 16 ++++--- src/soc/mediatek/common/mtk_mipi_cphy.c | 26 +++++------ src/soc/mediatek/common/mtk_mipi_dphy.c | 4 +- src/soc/mediatek/mt8173/dsi.c | 37 +++++++-------- 6 files changed, 70 insertions(+), 65 deletions(-) diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c index 66a5aaf2e1..5ee8985dfd 100644 --- a/src/soc/mediatek/common/dsi_common.c +++ b/src/soc/mediatek/common/dsi_common.c @@ -290,7 +290,7 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, edid->mode.va << DSI_SIZE_CON_HEIGHT_SHIFT | hactive << DSI_SIZE_CON_WIDTH_SHIFT); if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy) - mtk_dsi_cphy_enable_cmdq_6byte(); + mtk_dsi_cphy_enable_cmdq_6byte(dsi0); } static void mtk_dsi_start(void) @@ -385,8 +385,8 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, if (!data_rate) return -1; - mtk_dsi_configure_mipi_tx(data_rate, lanes, is_cphy); - mtk_dsi_reset(); + mtk_dsi_configure_mipi_tx(mipi_tx0, data_rate, lanes, is_cphy); + mtk_dsi_reset(dsi0); struct mtk_phy_timing phy_timing = {}; if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy) mtk_dsi_cphy_timing(data_rate, &phy_timing); diff --git a/src/soc/mediatek/common/dsi_v1.c b/src/soc/mediatek/common/dsi_v1.c index 030f034052..9d41104d82 100644 --- a/src/soc/mediatek/common/dsi_v1.c +++ b/src/soc/mediatek/common/dsi_v1.c @@ -6,7 +6,8 @@ #include #include -void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy) +void mtk_dsi_configure_mipi_tx(struct mipi_tx_regs *mipi_tx_reg, + u32 data_rate, u32 lanes, bool is_cphy) { unsigned int txdiv0; u64 pcw; @@ -28,47 +29,48 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy) } if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy) - mtk_dsi_cphy_lane_sel_setting(); + mtk_dsi_cphy_lane_sel_setting(mipi_tx_reg); - clrbits32(&mipi_tx0->pll_con4, BIT(11) | BIT(10)); - setbits32(&mipi_tx0->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); + clrbits32(&mipi_tx_reg->pll_con4, BIT(11) | BIT(10)); + setbits32(&mipi_tx_reg->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); udelay(30); - clrbits32(&mipi_tx0->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); + clrbits32(&mipi_tx_reg->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); pcw = (u64)data_rate * (1 << txdiv0); pcw <<= 24; pcw /= CLK26M_HZ; - write32(&mipi_tx0->pll_con0, pcw); - clrsetbits32(&mipi_tx0->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); + write32(&mipi_tx_reg->pll_con0, pcw); + clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); udelay(30); - setbits32(&mipi_tx0->pll_con1, RG_DSI_PLL_EN); + setbits32(&mipi_tx_reg->pll_con1, RG_DSI_PLL_EN); /* BG_LPF_EN / BG_CORE_EN */ - write32(&mipi_tx0->lane_con, 0x3FFF0180); + write32(&mipi_tx_reg->lane_con, 0x3FFF0180); udelay(40); - write32(&mipi_tx0->lane_con, 0x3FFF00C0); + write32(&mipi_tx_reg->lane_con, 0x3FFF00C0); if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy) - mtk_dsi_cphy_enable(); + mtk_dsi_cphy_enable(mipi_tx_reg); /* Switch OFF each Lane */ - clrbits32(&mipi_tx0->d0_sw_ctl_en, DSI_SW_CTL_EN); - clrbits32(&mipi_tx0->d1_sw_ctl_en, DSI_SW_CTL_EN); - clrbits32(&mipi_tx0->d2_sw_ctl_en, DSI_SW_CTL_EN); - clrbits32(&mipi_tx0->d3_sw_ctl_en, DSI_SW_CTL_EN); - clrbits32(&mipi_tx0->ck_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx_reg->d0_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx_reg->d1_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx_reg->d2_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx_reg->d3_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx_reg->ck_sw_ctl_en, DSI_SW_CTL_EN); if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy) - mtk_dsi_cphy_disable_ck_mode(); + mtk_dsi_cphy_disable_ck_mode(mipi_tx_reg); else - mtk_dsi_dphy_disable_ck_mode(); + mtk_dsi_dphy_disable_ck_mode(mipi_tx_reg); + } -void mtk_dsi_reset(void) +void mtk_dsi_reset(struct dsi_regs *dsi_reg) { - write32(&dsi0->dsi_force_commit, + write32(&dsi_reg->dsi_force_commit, DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS); - write32(&dsi0->dsi_con_ctrl, 1); - write32(&dsi0->dsi_con_ctrl, 0); + write32(&dsi_reg->dsi_con_ctrl, 1); + write32(&dsi_reg->dsi_con_ctrl, 0); } diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index c166f62e2f..e06701f490 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -9,6 +9,7 @@ #include #include #include +#include /* DSI_INTSTA */ enum { @@ -160,7 +161,7 @@ struct mtk_phy_timing { }; /* Functions that each SOC should provide. */ -void mtk_dsi_reset(void); +void mtk_dsi_reset(struct dsi_regs *dsi_reg); /* Functions as weak no-ops that can be overridden. */ void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing); @@ -169,17 +170,18 @@ void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing); * DSI-internal APIs provided in common/dsi_common.c, common/dsi_v1.c, * and common/mtk_mipi_{c/d}phy.c */ -void mtk_dsi_cphy_enable(void); -void mtk_dsi_cphy_enable_cmdq_6byte(void); -void mtk_dsi_cphy_lane_sel_setting(void); +void mtk_dsi_cphy_enable(struct mipi_tx_regs *mipi_tx_reg); +void mtk_dsi_cphy_enable_cmdq_6byte(struct dsi_regs *dsi_reg); +void mtk_dsi_cphy_lane_sel_setting(struct mipi_tx_regs *mipi_tx_reg); void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing); void mtk_dsi_cphy_vdo_timing(const u32 lanes, const struct edid *edid, const struct mtk_phy_timing *phy_timing, const u32 bytes_per_pixel, const u32 hbp, const u32 hfp, s32 *hbp_byte, s32 *hfp_byte, u32 *hsync_active_byte); -void mtk_dsi_cphy_disable_ck_mode(void); -void mtk_dsi_dphy_disable_ck_mode(void); +void mtk_dsi_cphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg); +void mtk_dsi_dphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg); void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing); -void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy); +void mtk_dsi_configure_mipi_tx(struct mipi_tx_regs *mipi_tx_reg, + u32 data_rate, u32 lanes, bool is_cphy); #endif /* SOC_MEDIATEK_DSI_COMMON_H */ diff --git a/src/soc/mediatek/common/mtk_mipi_cphy.c b/src/soc/mediatek/common/mtk_mipi_cphy.c index 8578d84e4e..3e78376951 100644 --- a/src/soc/mediatek/common/mtk_mipi_cphy.c +++ b/src/soc/mediatek/common/mtk_mipi_cphy.c @@ -17,29 +17,29 @@ #define MIPITX_CPHY_LANE_SEL2_SETTING 0x68543102 #define MIPITX_CPHY_LANE_SEL3_SETTING 0x00000007 -void mtk_dsi_cphy_lane_sel_setting(void) +void mtk_dsi_cphy_lane_sel_setting(struct mipi_tx_regs *mipi_tx_reg) { - write32(&mipi_tx0->phy_sel[0], MIPITX_CPHY_LANE_SEL0_SETTING); - write32(&mipi_tx0->phy_sel[1], MIPITX_CPHY_LANE_SEL1_SETTING); - write32(&mipi_tx0->phy_sel[2], MIPITX_CPHY_LANE_SEL2_SETTING); - write32(&mipi_tx0->phy_sel[3], MIPITX_CPHY_LANE_SEL3_SETTING); + write32(&mipi_tx_reg->phy_sel[0], MIPITX_CPHY_LANE_SEL0_SETTING); + write32(&mipi_tx_reg->phy_sel[1], MIPITX_CPHY_LANE_SEL1_SETTING); + write32(&mipi_tx_reg->phy_sel[2], MIPITX_CPHY_LANE_SEL2_SETTING); + write32(&mipi_tx_reg->phy_sel[3], MIPITX_CPHY_LANE_SEL3_SETTING); } -void mtk_dsi_cphy_enable(void) +void mtk_dsi_cphy_enable(struct mipi_tx_regs *mipi_tx_reg) { - setbits32(&mipi_tx0->lane_con, DSI_CPHY_EN); + setbits32(&mipi_tx_reg->lane_con, DSI_CPHY_EN); } -void mtk_dsi_cphy_disable_ck_mode(void) +void mtk_dsi_cphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg) { - clrsetbits32(&mipi_tx0->voltage_sel, DSI_HSTX_LDO_REF_SEL, 0xF << 6); - clrbits32(&mipi_tx0->ck_ckmode_en, DSI_CK_CKMODE_EN); - setbits32(&mipi_tx0->lane_con, DE_EMPHASIS_EN); + clrsetbits32(&mipi_tx_reg->voltage_sel, DSI_HSTX_LDO_REF_SEL, 0xF << 6); + clrbits32(&mipi_tx_reg->ck_ckmode_en, DSI_CK_CKMODE_EN); + setbits32(&mipi_tx_reg->lane_con, DE_EMPHASIS_EN); } -void mtk_dsi_cphy_enable_cmdq_6byte(void) +void mtk_dsi_cphy_enable_cmdq_6byte(struct dsi_regs *dsi_reg) { - clrbits32(&dsi0->dsi_cmd_type1_hs, CMD_CPHY_6BYTE_EN); + clrbits32(&dsi_reg->dsi_cmd_type1_hs, CMD_CPHY_6BYTE_EN); } void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing) diff --git a/src/soc/mediatek/common/mtk_mipi_dphy.c b/src/soc/mediatek/common/mtk_mipi_dphy.c index 3ebaa40109..6f161002db 100644 --- a/src/soc/mediatek/common/mtk_mipi_dphy.c +++ b/src/soc/mediatek/common/mtk_mipi_dphy.c @@ -3,7 +3,7 @@ #include #include -void mtk_dsi_dphy_disable_ck_mode(void) +void mtk_dsi_dphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg) { - setbits32(&mipi_tx0->ck_ckmode_en, DSI_CK_CKMODE_EN); + setbits32(&mipi_tx_reg->ck_ckmode_en, DSI_CK_CKMODE_EN); } diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index 3e87ba448a..8c1b02d3d6 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -7,14 +7,15 @@ #include #include -void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy) +void mtk_dsi_configure_mipi_tx(struct mipi_tx_regs *mipi_tx_reg, u32 data_rate, + u32 lanes, bool is_cphy) { u32 txdiv0, txdiv1; u64 pcw; u32 reg; int i; - reg = read32(&mipi_tx0->dsi_bg_con); + reg = read32(&mipi_tx_reg->dsi_bg_con); reg = (reg & (~RG_DSI_V02_SEL)) | (4 << 20); reg = (reg & (~RG_DSI_V032_SEL)) | (4 << 17); @@ -24,19 +25,19 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy) reg = (reg & (~RG_DSI_V12_SEL)) | (4 << 5); reg |= RG_DSI_BG_CKEN; reg |= RG_DSI_BG_CORE_EN; - write32(&mipi_tx0->dsi_bg_con, reg); + write32(&mipi_tx_reg->dsi_bg_con, reg); udelay(30); - clrsetbits32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, + clrsetbits32(&mipi_tx_reg->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); - setbits32(&mipi_tx0->dsi_con, + setbits32(&mipi_tx_reg->dsi_con, RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); - clrsetbits32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, + clrsetbits32(&mipi_tx_reg->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON); - clrbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + clrbits32(&mipi_tx_reg->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); if (data_rate > 500 * MHz) { txdiv0 = 0; @@ -57,7 +58,7 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy) txdiv1 = 2; } - clrsetbits32(&mipi_tx0->dsi_pll_con0, + clrsetbits32(&mipi_tx_reg->dsi_pll_con0, RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); @@ -71,27 +72,27 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy) */ pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24; pcw /= 13 * MHz; - write32(&mipi_tx0->dsi_pll_con2, pcw); + write32(&mipi_tx_reg->dsi_pll_con2, pcw); - setbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); + setbits32(&mipi_tx_reg->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); - setbits32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); + setbits32(&mipi_tx_reg->dsi_clock_lane, LDOOUT_EN); for (i = 0; i < lanes; i++) - setbits32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); + setbits32(&mipi_tx_reg->dsi_data_lane[i], LDOOUT_EN); - setbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + setbits32(&mipi_tx_reg->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); udelay(40); - clrbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); - clrbits32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); + clrbits32(&mipi_tx_reg->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); + clrbits32(&mipi_tx_reg->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); } -void mtk_dsi_reset(void) +void mtk_dsi_reset(struct dsi_regs *dsi_reg) { - setbits32(&dsi0->dsi_con_ctrl, 3); - clrbits32(&dsi0->dsi_con_ctrl, 1); + setbits32(&dsi_reg->dsi_con_ctrl, 3); + clrbits32(&dsi_reg->dsi_con_ctrl, 1); } void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)