From 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa Mon Sep 17 00:00:00 2001
From: Duncan Laurie <dlaurie@chromium.org>
Date: Thu, 1 May 2014 14:48:52 -0700
Subject: [PATCH] broadwell: Clean up SMBUS code in romstage and ramstage

romstage: Move the smbus enable code into reg_script format and call
the script with the PCH_DEV_SMBUS device.

ramstage: Use appropriate headers.

both: Change use of old SMBUS_IO_BASE to SMBUS_BASE ADDRESS.

BUG=chrome-os-partner:28234
TEST=None

Change-Id: Icf8c70810f86fc56d0f595a80b6d70361f6f7cd8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199191
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/broadwell/romstage/smbus.c | 50 ++++++++++--------------
 src/soc/intel/broadwell/smbus.c          |  9 +++--
 2 files changed, 25 insertions(+), 34 deletions(-)

diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c
index 6bab91b9f7..2bc14922ab 100644
--- a/src/soc/intel/broadwell/romstage/smbus.c
+++ b/src/soc/intel/broadwell/romstage/smbus.c
@@ -22,41 +22,31 @@
 #include <console/console.h>
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
-#include "pch.h"
-#include "smbus.h"
+#include <reg_script.h>
+#include <broadwell/iomap.h>
+#include <broadwell/pci_devs.h>
+#include <broadwell/smbus.h>
+#include <broadwell/romstage.h>
+
+static const struct reg_script smbus_init_script[] = {
+	/* Set SMBUS I/O base address */
+	REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1),
+	/* Set SMBUS enable */
+	REG_PCI_WRITE8(HOSTC, HST_EN),
+	/* Enable I/O access */
+	REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO),
+	/* Disable interrupts */
+	REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
+	/* Clear errors */
+	REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
+};
 
 void enable_smbus(void)
 {
-	device_t dev;
-
-	/* Set the SMBus device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x3);
-
-	/* Check to make sure we've got the right device. */
-	if (pci_read_config16(dev, 0x0) != 0x8086) {
-		die("SMBus controller not found!");
-	}
-
-	/* Set SMBus I/O base. */
-	pci_write_config32(dev, SMB_BASE,
-			   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
-
-	/* Set SMBus enable. */
-	pci_write_config8(dev, HOSTC, HST_EN);
-
-	/* Set SMBus I/O space enable. */
-	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
-
-	/* Disable interrupt generation. */
-	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* Clear any lingering errors, so transactions can run. */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	print_debug("SMBus controller enabled.\n");
+	reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
 }
 
 int smbus_read_byte(unsigned device, unsigned address)
 {
-	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+	return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address);
 }
-
diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c
index 135ec45cc4..a1dbdfecc8 100644
--- a/src/soc/intel/broadwell/smbus.c
+++ b/src/soc/intel/broadwell/smbus.c
@@ -18,17 +18,18 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <arch/io.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/path.h>
 #include <device/smbus.h>
+#include <device/smbus_def.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
-#include "pch.h"
-#include "smbus.h"
+#include <broadwell/iomap.h>
 #include <broadwell/ramstage.h>
+#include <broadwell/smbus.h>
 
 static void pch_smbus_init(device_t dev)
 {
@@ -79,7 +80,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
 static void smbus_read_resources(device_t dev)
 {
 	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
-	res->base = SMBUS_IO_BASE;
+	res->base = SMBUS_BASE_ADDRESS;
 	res->size = 32;
 	res->limit = res->base + res->size - 1;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |