From 6aa934f5c5945974df3aaa0f1162562f6d6b668d Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 30 Oct 2014 15:25:42 -0700 Subject: [PATCH] auron: Declare TPM in devicetree.cb and include ACPI device This adds the TPM device to the devicetree and configures an active high edge triggered interrupt at IRQ10 and adds the ACPI Device for the TPM into the DSDT. It also cleans up the EC PNP ID to use the EISAID for an EC since there are now two PNP devices declared, and removes the unused ENABLE_TPM define at the top of the DSDT. BUG=chrome-os-partner:33385 BRANCH=auron TEST=same change tested on broadwell samus device CQ-DEPEND=CL:226661 Change-Id: I4e106a3ae4f9fb4042ce75f010a68d91bbd4b8a6 Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/226664 Reviewed-by: Aaron Durbin --- src/mainboard/google/auron/acpi/mainboard.asl | 8 ++++++++ src/mainboard/google/auron/acpi_tables.c | 3 --- src/mainboard/google/auron/devicetree.cb | 13 ++++++++----- src/mainboard/google/auron/dsdt.asl | 2 -- 4 files changed, 16 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index 488401c594..547cdb03f2 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -44,6 +44,14 @@ Scope (\_SB) } } +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include +} + Scope (\_SB.PCI0.I2C0) { Device (ETPA) diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index eefcd3d972..efb17dc730 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -45,9 +45,6 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* Disable USB ports in S5 */ gnvs->s5u0 = 0; - /* TPM Present */ - gnvs->tpmp = 1; - gnvs->tmps = TEMPERATURE_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 045aa795e9..77e71b8d3d 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -90,13 +90,16 @@ chip soc/intel/broadwell device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 end end + chip ec/google/chromeec + device pnp 0c09.0 on end + end end # LPC bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 off end # SMBus diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 19a5204bf1..f7246612ea 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ENABLE_TPM - DefinitionBlock( "dsdt.aml", "DSDT",