erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Here we start to see the good design of 3. In v2, there were pci ops in

Browse source 
all stages, blighting everything with the same code, compiled different 
ways. In this change, we see that:
- basic conf ops are compiled into stage0, where they are used. 
- they are called directly from initram
- they are used to initialize the pci_cf8_conf1 structure in stage 2, 
   but the call still goes to stage0!

one copy of the code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@752 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-08-13 02:41:29 +00:00
commit 6a732582c7
3 changed files with 32 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

10
include/device/pci_ops.h
View file

@ -21,6 +21,7 @@
#include <types.h>
#include <device/device.h>
#include <pci_ops.h>
#include <shared.h>
u8 pci_read_config8(struct device * dev, unsigned where);
u16 pci_read_config16(struct device * dev, unsigned where);
@ -29,4 +30,13 @@ void pci_write_config8(struct device * dev, unsigned where, u8 val);
void pci_write_config16(struct device * dev, unsigned where, u16 val);
void pci_write_config32(struct device * dev, unsigned where, u32 val);
SHARED(pci_conf1_read_config8, u8, u32 bdf, int where);
SHARED(pci_conf1_read_config16, u16, u32 bdf, int where);
SHARED(pci_conf1_read_config32, u32, u32 bdf, int where);
SHARED(pci_conf1_write_config8, void , u32 bdf, int where, u8 value);
SHARED(pci_conf1_write_config16, void, u32 bdf, int where, u16 value);
SHARED(pci_conf1_write_config32, void, u32 bdf, int where, u32 value);
SHARED(pci_conf1_find_on_bus, int, u16 bus, u16 vid, u16 did, u32 *busdevfn);
SHARED(pci_conf1_find_device, int, u16 vid, u16 did, u32 * dev);
#endif /* DEVICE_PCI_OPS_H */