From 69e6d96aad68b20ca35ff2bdcdcc62c777706d85 Mon Sep 17 00:00:00 2001 From: Megha Verma Date: Thu, 24 Jul 2025 12:12:49 +0530 Subject: [PATCH] mb/google/fatcat: Configure host command ranges for FATCAT4ES variant The commit introduces changes to support the FATCAT4ES board variant by updating the EC command range configuration. The changes updates the gen1_dec register to configure correctly to accomdate the FATCAT4ES variant which ensures the ec-host communication should not fail. Also it ensures other conditional checks in the EC header file for enabling this new variant. BUG=b:432676108 TEST=Build with the FATCAT4ES configuration and verify ec host communication is not failing. Change-Id: I5c84dc2161847f9fe4316c0e63aa876696947423 Signed-off-by: Megha Verma Reviewed-on: https://review.coreboot.org/c/coreboot/+/88552 Reviewed-by: Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- .../google/fatcat/variants/baseboard/fatcat/devicetree.cb | 2 +- .../fatcat/variants/baseboard/fatcat/include/baseboard/ec.h | 4 +++- src/mainboard/google/fatcat/variants/fatcat/gpio.c | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index 5c73dee1e0..6eded7c12f 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -8,7 +8,7 @@ chip soc/intel/pantherlake # EC host command ranges are in 0x800-0x807 & 0x200-0x20f # For Fatcat variants with ITE/Nuvoton EC: # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCATISH) ? 0x00040801 : 0x00fc0801" + register "gen1_dec" = "CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCAT4ES) || CONFIG(BOARD_GOOGLE_FATCATISH) ? 0x00040801 : 0x00fc0801" register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h index 7fff4dae75..8f583e9308 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h @@ -75,7 +75,9 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -#if !CONFIG(BOARD_GOOGLE_FATCAT) && !CONFIG(BOARD_GOOGLE_FATCATISH) +#if !CONFIG(BOARD_GOOGLE_FATCAT) \ + && !CONFIG(BOARD_GOOGLE_FATCAT4ES) \ + && !CONFIG(BOARD_GOOGLE_FATCATISH) #define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ #define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */ #endif diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index b31ba05437..4b6462a60e 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -196,7 +196,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_E03, 1, PLTRST), /* GPP_E06: SECURE_CAM_SW */ PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI), -#if CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCATISH) +#if CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCAT4ES) || CONFIG(BOARD_GOOGLE_FATCATISH) /* GPP_E07: Not used */ PAD_NC(GPP_E07, NONE), #else