diff --git a/src/soc/intel/broadwell/romstage/fsp_1_1.inc b/src/soc/intel/broadwell/romstage/fsp_1_1.inc
index fdb7df1e2e..2cdea6924a 100644
--- a/src/soc/intel/broadwell/romstage/fsp_1_1.inc
+++ b/src/soc/intel/broadwell/romstage/fsp_1_1.inc
@@ -157,9 +157,82 @@ before_romstage:
 	call  romstage_main
 
 	/*
+	 * eax:  New stack address
 	 * ebx:  FSP_INFO_HEADER address
 	 */
 
+	/* Switch to the stack in RAM */
+	movl	%eax, %esp
+
+	/* Calculate TempRamExit entry into FSP */
+	movl	%ebx, %ebp
+	mov	0x40(%ebp), %eax
+	add	0x1c(%ebp), %eax
+
+	/* Build the call frame */
+	movl	%esp, %ebx
+	pushl	$0
+
+	/* Call TempRamExit */
+	call	*%eax
+
+	/*
+	 * ebx:  FSP_INFO_HEADER address
+	 */
+
+	/* Get number of MTRRs. */
+	popl	%ebx
+	movl	$MTRRphysBase_MSR(0), %ecx
+1:
+	testl	%ebx, %ebx
+	jz	1f
+
+	/* Low 32 bits of MTRR base. */
+	popl	%eax
+	/* Upper 32 bits of MTRR base. */
+	popl	%edx
+	/* Write MTRR base. */
+	wrmsr
+	inc	%ecx
+	/* Low 32 bits of MTRR mask. */
+	popl	%eax
+	/* Upper 32 bits of MTRR mask. */
+	popl	%edx
+	/* Write MTRR mask. */
+	wrmsr
+	inc	%ecx
+
+	dec	%ebx
+	jmp	1b
+1:
+	post_code(0x39)
+
+	/* And enable cache again after setting MTRRs. */
+	movl	%cr0, %eax
+	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+	movl	%eax, %cr0
+
+	post_code(0x3a)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	post_code(0x3b)
+
+	/* Invalidate the cache again. */
+	invd
+
+	post_code(0x3c)
+
+__main:
+	post_code(POST_PREPARE_RAMSTAGE)
+	cld			/* Clear direction flag. */
+	call	romstage_after_car
+
+
 	movb  $0x69, %ah
 	jmp   .Lhlt
 
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 2f8b04a0e9..eb29032246 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -46,6 +46,7 @@
 asmlinkage void *romstage_main(unsigned int bist,
 				uint32_t tsc_low, uint32_t tsc_hi)
 {
+	void *top_of_stack;
 	struct romstage_params rp = {
 		.bist = bist,
 		.pei_data = NULL,
@@ -98,7 +99,13 @@ asmlinkage void *romstage_main(unsigned int bist,
 	/* Call into mainboard. */
 	mainboard_romstage_entry(&rp);
 
-	return setup_stack_and_mttrs();
+	top_of_stack = setup_stack_and_mttrs();
+
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
+	printk(BIOS_DEBUG, "Calling FspTempRamExit API\n");
+#endif	/* CONFIG_PLATFORM_USES_FSP */
+
+	return top_of_stack;
 }
 
 static inline void chromeos_init(int prev_sleep_state)
@@ -176,14 +183,6 @@ void romstage_common(struct romstage_params *params)
 	raminit(params, pei_data);
 	timestamp_add_now(TS_AFTER_INITRAM);
 
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
-/* TODO: Remove this code.  Temporary code to hang after FspMemoryInit API */
-	printk(BIOS_DEBUG, "Hanging in romstage_common!\n");
-	post_code(0x35);
-	while (1)
-		;
-#endif	/* CONFIG_PLATFORM_USES_FSP */
-
 	printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
 	       pei_data->data_to_save_size);
 
@@ -207,8 +206,20 @@ void romstage_common(struct romstage_params *params)
 
 void asmlinkage romstage_after_car(void)
 {
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
+	printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
+#endif	/* CONFIG_PLATFORM_USES_FSP */
+
 	timestamp_add_now(TS_END_ROMSTAGE);
 
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
+/* TODO: Remove this code.  Temporary code to hang after FSP TempRamInit API */
+	printk(BIOS_ERR, "Hanging in romstage_after_car!\n");
+	post_code(0x35);
+	while (1)
+		;
+#endif	/* CONFIG_PLATFORM_USES_FSP */
+
 	/* Run vboot verification if configured. */
 	vboot_verify_firmware(romstage_handoff_find_or_add());