soc/amd/cezanne: Set up SoC-specific XHCI definitions

Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI.

BRANCH=guybrush
BUG=b:186792595
TEST=builds

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67939
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/Kconfig

@@ -70,6 +70,7 @@ config SOC_AMD_CEZANNE
 	select SOC_AMD_COMMON_FSP_DMI_TABLES
 	select SOC_AMD_COMMON_FSP_PCI
 	select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
+	select SOC_AMD_COMMON_BLOCK_XHCI
 	select SSE2
 	select UDK_2017_BINDING
 	select USE_DDR4

src/soc/amd/cezanne/include/soc/xhci.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_XHCI_H
+#define AMD_CEZANNE_XHCI_H
+
+#include <device/device.h>
+
+#define SOC_XHCI_0 DEV_PTR(xhci_0)
+#define SOC_XHCI_1 DEV_PTR(xhci_1)
+#define SOC_XHCI_2 NULL
+#define SOC_XHCI_3 NULL
+#define SOC_XHCI_4 NULL
+#define SOC_XHCI_5 NULL
+#define SOC_XHCI_6 NULL
+#define SOC_XHCI_7 NULL
+
+#endif /* AMD_CEZANNE_XHCI_H */