From 696391a76339b9fa4f2214ef003c73a4a8ac542c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Wed, 12 Mar 2025 12:01:16 +0100 Subject: [PATCH] mb/novacustom/mtl-h/ramstage.c: Set Port Reset FSP UPDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable Port Reset on USB lanes corresponding to Type-C ports on the mainboard. Change-Id: Id9adc8827f3393e419118efda91c06c43ebb2ccb Signed-off-by: Michał Kopeć Reviewed-on: https://review.coreboot.org/c/coreboot/+/86843 Reviewed-by: Krystian Hebel Tested-by: build bot (Jenkins) --- src/mainboard/novacustom/mtl-h/ramstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c index cd7031ba01..19d14a6e1a 100644 --- a/src/mainboard/novacustom/mtl-h/ramstage.c +++ b/src/mainboard/novacustom/mtl-h/ramstage.c @@ -39,4 +39,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->CnviClkreqPinMux = 0x394CE605; // GPP_F05 params->LidStatus = dasharo_ec_get_lid_state(); + + params->PortResetMessageEnable[1] = 1; + params->PortResetMessageEnable[5] = 1; }