From 69599da6c4cdb7a9ef078fc1423ecd9c5d5d8c8d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 24 Jun 2013 03:14:41 -0700 Subject: [PATCH] exynos5420: Clock the mmc blocks off of the mpll. The exynos manual suggests hooking the mmc ip blocks to the mpll. They had been set to use a different pll. This changes them over and modifies the divider so that the frequency stays the same. BUG=chrome-os-partner:19420 TEST=Built and booted into depthcharge on pit. BRANCH=None Change-Id: I9b473b683c5806a49c9eba91807baa0b58c9c9dd Signed-off-by: Gabe Black Reviewed-on: https://gerrit.chromium.org/gerrit/59732 Reviewed-by: Ronald G. Minnich Commit-Queue: Gabe Black Tested-by: Gabe Black --- src/cpu/samsung/exynos5420/setup.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index 7d63772832..e89ed8eee4 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -222,7 +222,7 @@ struct exynos5_phy_control; #define CLK_DIV_CPU0_VAL 0x01440020 /* CLK_SRC_TOP */ -#define CLK_SRC_TOP0_VAL 0x12221222 +#define CLK_SRC_TOP0_VAL 0x12222222 #define CLK_SRC_TOP1_VAL 0x00100200 #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 @@ -231,7 +231,7 @@ struct exynos5_phy_control; #define CLK_SRC_TOP7_VAL 0x00022200 /* CLK_DIV_TOP */ -#define CLK_DIV_TOP0_VAL 0x23712311 +#define CLK_DIV_TOP0_VAL 0x23713311 #define CLK_DIV_TOP1_VAL 0x13100B00 #define CLK_DIV_TOP2_VAL 0x11101100