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nb/intel/sandybridge: Add a chipset devicetree

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This only moves CPU configuration to a common place. Other PCI devices
can be done in follow-ups.

Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2021-08-11 13:42:40 +02:00 • committed by Martin L Roth
commit 691d58f999
43 changed files with 25 additions and 367 deletions
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1
src/mainboard/roda/rv11/variants/rv11/devicetree.cb
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@ -23,7 +23,6 @@ chip northbridge/intel/sandybridge
device lapic 0 on end
device lapic 0xacac off end
register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1)
register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6)
register "acpi_c3" = "0"
end

1
src/mainboard/roda/rv11/variants/rw11/devicetree.cb
View file

@ -23,7 +23,6 @@ chip northbridge/intel/sandybridge
device lapic 0 on end
device lapic 0xacac off end
register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1)
register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6)
register "acpi_c3" = "0"
end