From 690d5777c750c831b3008719ef3868d573c977b1 Mon Sep 17 00:00:00 2001 From: Greg Watson Date: Tue, 15 Apr 2003 18:57:11 +0000 Subject: [PATCH] more ppc --- src/arch/ppc/include/arch/io.h | 182 ++++++++++++++ src/southbridge/winbond/w83c553/w83c553f.c | 269 +++++++++++++++++++++ src/southbridge/winbond/w83c553/w83c553f.h | 179 ++++++++++++++ 3 files changed, 630 insertions(+) create mode 100644 src/arch/ppc/include/arch/io.h create mode 100644 src/southbridge/winbond/w83c553/w83c553f.c create mode 100644 src/southbridge/winbond/w83c553/w83c553f.h diff --git a/src/arch/ppc/include/arch/io.h b/src/arch/ppc/include/arch/io.h new file mode 100644 index 0000000000..6df64830df --- /dev/null +++ b/src/arch/ppc/include/arch/io.h @@ -0,0 +1,182 @@ +/* + * BK Id: SCCS/s.io.h 1.14 10/16/01 15:58:42 trini + */ +#ifndef _PPC_IO_H +#define _PPC_IO_H +#include + +#define SIO_CONFIG_RA 0x398 +#define SIO_CONFIG_RD 0x399 + +#define SLOW_DOWN_IO + +#define PMAC_ISA_MEM_BASE 0 +#define PMAC_PCI_DRAM_OFFSET 0 +#define CHRP_ISA_IO_BASE 0xf8000000 +#define CHRP_ISA_MEM_BASE 0xf7000000 +#define CHRP_PCI_DRAM_OFFSET 0 +#define PREP_ISA_IO_BASE 0x80000000 +#define PREP_ISA_MEM_BASE 0xc0000000 +#define PREP_PCI_DRAM_OFFSET 0x80000000 + +#define _IO_BASE 0xfe000000 + +#define readb(addr) in_8((volatile u8 *)(addr)) +#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) +#define readw(addr) in_le16((volatile u16 *)(addr)) +#define readl(addr) in_le32((volatile u32 *)(addr)) +#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) +#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) + + +#define __raw_readb(addr) (*(volatile unsigned char *)(addr)) +#define __raw_readw(addr) (*(volatile unsigned short *)(addr)) +#define __raw_readl(addr) (*(volatile unsigned int *)(addr)) +#define __raw_writeb(v, addr) (*(volatile unsigned char *)(addr) = (v)) +#define __raw_writew(v, addr) (*(volatile unsigned short *)(addr) = (v)) +#define __raw_writel(v, addr) (*(volatile unsigned int *)(addr) = (v)) + +/* + * The insw/outsw/insl/outsl macros don't do byte-swapping. + * They are only used in practice for transferring buffers which + * are arrays of bytes, and byte-swapping is not appropriate in + * that case. - paulus + */ +#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define inb(port) in_8((u8 *)((port)+_IO_BASE)) +#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) +#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) + +#define inb_p(port) inb((port)) +#define outb_p(val, port) outb((val), (port)) +#define inw_p(port) inw((port)) +#define outw_p(val, port) outw((val), (port)) +#define inl_p(port) inl((port)) +#define outl_p(val, port) outl((val), (port)) + +extern void _insb(volatile u8 *port, void *buf, int ns); +extern void _outsb(volatile u8 *port, const void *buf, int ns); +extern void _insw(volatile u16 *port, void *buf, int ns); +extern void _outsw(volatile u16 *port, const void *buf, int ns); +extern void _insl(volatile u32 *port, void *buf, int nl); +extern void _outsl(volatile u32 *port, const void *buf, int nl); +extern void _insw_ns(volatile u16 *port, void *buf, int ns); +extern void _outsw_ns(volatile u16 *port, const void *buf, int ns); +extern void _insl_ns(volatile u32 *port, void *buf, int nl); +extern void _outsl_ns(volatile u32 *port, const void *buf, int nl); + +/* + * The *_ns versions below don't do byte-swapping. + * Neither do the standard versions now, these are just here + * for older code. + */ +#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + + +#define IO_SPACE_LIMIT ~0 + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + +/* + * Enforce In-order Execution of I/O: + * Acts as a barrier to ensure all previous I/O accesses have + * completed before any further ones are issued. + */ +extern inline void eieio(void) +{ + __asm__ __volatile__ ("eieio" : : : "memory"); +} + +/* Enforce in-order execution of data I/O. + * No distinction between read/write on PPC; use eieio for all three. + */ +#define iobarrier_rw() eieio() +#define iobarrier_r() eieio() +#define iobarrier_w() eieio() + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + */ +extern inline int in_8(volatile unsigned char *addr) +{ + int ret; + + __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_8(volatile unsigned char *addr, int val) +{ + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +extern inline int in_le16(volatile unsigned short *addr) +{ + int ret; + + __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline int in_be16(volatile unsigned short *addr) +{ + int ret; + + __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le16(volatile unsigned short *addr, int val) +{ + __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be16(volatile unsigned short *addr, int val) +{ + __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +extern inline unsigned in_le32(volatile unsigned *addr) +{ + unsigned ret; + + __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline unsigned in_be32(volatile unsigned *addr) +{ + unsigned ret; + + __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le32(volatile unsigned *addr, int val) +{ + __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be32(volatile unsigned *addr, int val) +{ + __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} +#endif diff --git a/src/southbridge/winbond/w83c553/w83c553f.c b/src/southbridge/winbond/w83c553/w83c553f.c new file mode 100644 index 0000000000..66e5b924c8 --- /dev/null +++ b/src/southbridge/winbond/w83c553/w83c553f.c @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Initialisation of the PCI-to-ISA bridge and disabling the BIOS + * write protection (for flash) in function 0 of the chip. + * Enabling function 1 (IDE controller of the chip. + */ + +#include +#include +#include +#include +#include "w83c553f.h" + +#ifndef CONFIG_ISA_MEM +#define CONFIG_ISA_MEM 0xFD000000 +#endif +#ifndef CONFIG_ISA_IO +#define CONFIG_ISA_IO 0xFE000000 +#endif + +#ifndef CONFIG_IDE_MAXBUS +#define CONFIG_IDE_MAXBUS 2 +#endif +#ifndef CONFIG_IDE_MAXDEVICE +#define CONFIG_IDE_MAXDEVICE (CONFIG_IDE_MAXBUS*2) +#endif + +u32 ide_bus_offset[CONFIG_IDE_MAXBUS]; + +void initialise_pic(void); +void initialise_dma(void); + +extern struct pci_ops pci_direct_ppc; + +void southbridge_early_init(void) +{ + struct pci_dev *devbusfn; + unsigned char reg8; + unsigned short reg16; + unsigned int reg32; + + /* + * Set ISA memory space + */ + pci_direct_ppc.read_byte(0, 0x58, WINBOND_IPADCR, ®8); + /* 16 MB ISA memory space */ + reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7); + reg8 &= ~IPADCR_MBE512; + pci_direct_ppc.read_byte(0, 0x58, WINBOND_IPADCR, reg8); +} + +void southbridge_init(void) +{ + struct pci_dev *devbusfn; + unsigned char reg8; + unsigned short reg16; + unsigned int reg32; + + devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0); + if (devbusfn == 0) + { + printk_info("Error: Cannot find W83C553F controller on any PCI bus\n"); + return; + } + + printk_info("Found W83C553F controller\n"); + + /* always enabled */ +#if 0 + pci_read_config_word(devbusfn, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + pci_write_config_word(devbusfn, PCI_COMMAND, reg16); +#endif + + /* + * Set ISA memory space + */ + pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8); + /* 16 MB ISA memory space */ + reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7); + reg8 &= ~IPADCR_MBE512; + pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8); + + /* + * Chip select: switch off BIOS write protection + */ + pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8); + reg8 |= CSCR_UBIOSCSE; + reg8 &= ~CSCR_BIOSWP; + pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8); + + /* + * Interrupt routing: + * - IDE -> INTC/INTD + * - INTA -> IRQ 5 + * - INTB -> IRQ 6 + * - INTC -> IRQ 7 + * - INTD -> IRQ 8 + */ + pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x0); + pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0x5678); + + /* + * Read IDE bus offsets from function 1 device. + * We must unmask the LSB indicating that it is an IO address. + */ + devbusfn = pci_find_device(W83C553F_VID, W83C553F_IDE, 0); + if (devbusfn == 0) + { + printk_info("Error: Cannot find W83C553F function 1 device\n"); + return; + } + + /* + * Switch off legacy IRQ for IDE and IDE port 1. + */ + pci_write_config_byte(devbusfn, 0x09, 0x8F); + + /* + * Set LEGIRQ (IDE->IRQD/E) + * Disable secondary port ~P1EN (?) + * Secondary port Mode 0 ~P1F16 + */ + pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32); + reg32 |= IDECSR_LEGIRQ; + reg32 &= ~(IDECSR_P1EN | IDECSR_P1F16); + pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32); + + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]); + ide_bus_offset[0] &= ~1; +#if CONFIG_IDE_MAXBUS > 1 + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]); + ide_bus_offset[1] &= ~1; +#endif + + /* + * Enable function 1, IDE -> busmastering and IO space access + */ + pci_read_config_word(devbusfn, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word(devbusfn, PCI_COMMAND, reg16); + + /* + * Initialise ISA interrupt controller + */ + initialise_pic(); + + /* + * Initialise DMA controller + */ + initialise_dma(); + + printk_info("W83C553F configuration complete\n"); +} + +void initialise_pic(void) +{ + outb(W83C553F_PIC1_ICW1, 0x11); + outb(W83C553F_PIC1_ICW2, 0x08); + outb(W83C553F_PIC1_ICW3, 0x04); + outb(W83C553F_PIC1_ICW4, 0x01); + outb(W83C553F_PIC1_OCW1, 0xfb); + outb(W83C553F_PIC1_ELC, 0x20); + + outb(W83C553F_PIC2_ICW1, 0x11); + outb(W83C553F_PIC2_ICW2, 0x08); + outb(W83C553F_PIC2_ICW3, 0x02); + outb(W83C553F_PIC2_ICW4, 0x01); + outb(W83C553F_PIC2_OCW1, 0xff); + outb(W83C553F_PIC2_ELC, 0xce); + + outb(W83C553F_TMR1_CMOD, 0x74); + + outb(W83C553F_PIC2_OCW1, 0x20); + outb(W83C553F_PIC1_OCW1, 0x20); + + outb(W83C553F_PIC2_OCW1, 0x2b); + outb(W83C553F_PIC1_OCW1, 0x2b); +} + +void initialise_dma(void) +{ + unsigned int channel; + unsigned int rvalue1, rvalue2; + + /* perform a H/W reset of the devices */ + + outb(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00); + outw(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000); + + /* initialise all channels to a sane state */ + + for (channel = 0; channel < 4; channel++) { + /* + * dependent upon the channel, setup the specifics: + * + * demand + * address-increment + * autoinitialize-disable + * verify-transfer + */ + + switch (channel) { + case 0: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL); + break; + case 1: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); + break; + case 2: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); + break; + case 3: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); + break; + default: + rvalue1 = 0x00; + rvalue2 = 0x00; + break; + } + + /* write to write mode registers */ + + outb(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF); + outw(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF); + } + + /* enable all channels */ + + outb(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00); + outw(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000); + /* + * initialize the global DMA configuration + * + * DACK# active low + * DREQ active high + * fixed priority + * channel group enable + */ + + outb(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00); + outw(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000); +} diff --git a/src/southbridge/winbond/w83c553/w83c553f.h b/src/southbridge/winbond/w83c553/w83c553f.h new file mode 100644 index 0000000000..b0f5bbf19a --- /dev/null +++ b/src/southbridge/winbond/w83c553/w83c553f.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + /* winbond access routines and defines*/ + +/* from the winbond data sheet - + The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. + Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. +*/ + +/*ISA bridge configuration space*/ + +#define W83C553F_VID 0x10AD +#define W83C553F_DID 0x0565 +#define W83C553F_IDE 0x0105 + +#define WINBOND_PCICONTR 0x40 /*pci control reg*/ +#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/ +#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/ +#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ +#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ +#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/ +#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ +#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ +#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ +#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ +#define WINBOND_CDR 0x4c /*Clock Divisor Register*/ +#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/ +#define WINBOND_ATSCR 0x4e /*AT System Control register*/ +#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/ +#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ +#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ +#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/ +#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/ + +#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/ + +#define IPADCR_MBE512 0x1 +#define IPADCR_MBE640 0x2 +#define IPADCR_IPATOM4 0x10 +#define IPADCR_IPATOM5 0x20 +#define IPADCR_IPATOM6 0x40 +#define IPADCR_IPATOM7 0x80 + +#define CSCR_UBIOSCSE 0x10 +#define CSCR_BIOSWP 0x20 + +#define IDECSR_P0EN 0x01 +#define IDECSR_P0F16 0x02 +#define IDECSR_P1EN 0x10 +#define IDECSR_P1F16 0x20 +#define IDECSR_LEGIRQ 0x800 + +/* + * Interrupt controller + */ +#define W83C553F_PIC1_ICW1 CONFIG_ISA_IO + 0x20 +#define W83C553F_PIC1_ICW2 CONFIG_ISA_IO + 0x21 +#define W83C553F_PIC1_ICW3 CONFIG_ISA_IO + 0x21 +#define W83C553F_PIC1_ICW4 CONFIG_ISA_IO + 0x21 +#define W83C553F_PIC1_OCW1 CONFIG_ISA_IO + 0x21 +#define W83C553F_PIC1_OCW2 CONFIG_ISA_IO + 0x20 +#define W83C553F_PIC1_OCW3 CONFIG_ISA_IO + 0x20 +#define W83C553F_PIC1_ELC CONFIG_ISA_IO + 0x4D0 +#define W83C553F_PIC2_ICW1 CONFIG_ISA_IO + 0xA0 +#define W83C553F_PIC2_ICW2 CONFIG_ISA_IO + 0xA1 +#define W83C553F_PIC2_ICW3 CONFIG_ISA_IO + 0xA1 +#define W83C553F_PIC2_ICW4 CONFIG_ISA_IO + 0xA1 +#define W83C553F_PIC2_OCW1 CONFIG_ISA_IO + 0xA1 +#define W83C553F_PIC2_OCW2 CONFIG_ISA_IO + 0xA0 +#define W83C553F_PIC2_OCW3 CONFIG_ISA_IO + 0xA0 +#define W83C553F_PIC2_ELC CONFIG_ISA_IO + 0x4D1 + +#define W83C553F_TMR1_CMOD CONFIG_ISA_IO + 0x43 + +/* + * DMA controller + */ +#define W83C553F_DMA1 CONFIG_ISA_IO + 0x000 /* channel 0 - 3 */ +#define W83C553F_DMA2 CONFIG_ISA_IO + 0x0C0 /* channel 4 - 7 */ + +/* command/status register bit definitions */ + +#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ +#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ +#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ +#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ + +#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */ +#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */ +#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */ +#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */ + +#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */ +#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */ +#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */ +#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */ + +/* mode register bit definitions */ + +#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */ +#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */ +#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */ +#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */ +#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */ +#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */ +#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */ +#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */ +#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */ +#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */ +#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */ +#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */ +#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */ +#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */ + +/* request register bit definitions */ + +#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */ +#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */ +#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */ +#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */ +#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */ + +/* write single mask bit register bit definitions */ + +#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */ +#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */ +#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */ +#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */ +#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */ + +/* read/write all mask bits register bit definitions */ + +#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */ +#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */ +#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */ +#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */ + +/* typedefs */ + +#define W83C553F_DMA1_CS 0x8 +#define W83C553F_DMA1_WR 0x9 +#define W83C553F_DMA1_WSMB 0xA +#define W83C553F_DMA1_WM 0xB +#define W83C553F_DMA1_CBP 0xC +#define W83C553F_DMA1_MC 0xD +#define W83C553F_DMA1_CM 0xE +#define W83C553F_DMA1_RWAMB 0xF + +#define W83C553F_DMA2_CS 0xD0 +#define W83C553F_DMA2_WR 0xD2 +#define W83C553F_DMA2_WSMB 0xD4 +#define W83C553F_DMA2_WM 0xD6 +#define W83C553F_DMA2_CBP 0xD8 +#define W83C553F_DMA2_MC 0xDA +#define W83C553F_DMA2_CM 0xDC +#define W83C553F_DMA2_RWAMB 0xDE + +void initialise_w83c553f(void);