From 68b0122472af27f38502d42a8a6c80678ddbbba6 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 1 May 2014 15:44:10 -0700 Subject: [PATCH] broadwell: Add CPU set_max_freq function for romstage This can be used to raise the core frequency to maximum, but it may not take effect until BIOS_RESET_CPL bit has been set. BUG=chrome-os-partner:28234 TEST=None Change-Id: I4841025bad4fa4ab61236e3d7f7f3172061ff39f Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/199362 Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/romstage/cpu.c | 49 +++++++++++++++++++++ src/soc/intel/broadwell/romstage/romstage.c | 2 + 2 files changed, 51 insertions(+) create mode 100644 src/soc/intel/broadwell/romstage/cpu.c diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c new file mode 100644 index 0000000000..e7139b807d --- /dev/null +++ b/src/soc/intel/broadwell/romstage/cpu.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +void set_max_freq(void) +{ + msr_t msr, perf_ctl, platform_info; + + /* Check for configurable TDP option */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + + if ((platform_info.hi >> 1) & 3) { + /* Set to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + + perf_ctl.hi = 0; + wrmsr(IA32_PERF_CTL, perf_ctl); + + printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); +} diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index f77f9141e0..84d1f11f5c 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -76,6 +76,8 @@ void * asmlinkage romstage_main(unsigned long bist, /* Print useful platform information */ report_platform_info(); + /* Set CPU frequency to maximum */ + set_max_freq(); /* Call into mainboard. */ mainboard_romstage_entry(&rp);