diff --git a/src/soc/amd/turin_poc/Kconfig b/src/soc/amd/turin_poc/Kconfig
index 55af8c71e6..8eadb04933 100644
--- a/src/soc/amd/turin_poc/Kconfig
+++ b/src/soc/amd/turin_poc/Kconfig
@@ -10,23 +10,39 @@ config SOC_SPECIFIC_OPTIONS
 	select ACPI_SOC_NVS
 	select ARCH_X86
 	select DEFAULT_X2APIC
+	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
+	select CACHE_MRC_SETTINGS
+	select DRIVERS_USB_ACPI
+	select DRIVERS_USB_PCI_XHCI
+	select GENERIC_GPIO_LIB
 	select HAVE_ACPI_TABLES
+	select HAVE_CF9_RESET
+	select HAVE_EM100_SUPPORT
 	select HAVE_X86_64_SUPPORT
-	select HAVE_SMI_HANDLER
+	select HAVE_SMI_HANDLER if !NO_SMM
+	select IDT_IN_EVERY_STAGE
+	select PARALLEL_MP_AP_WORK
+	select PROVIDES_ROM_SHARING
+	select RTC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACPI
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS
 	select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
 	select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
 	select SOC_AMD_COMMON_BLOCK_ACPI_MADT
 	select SOC_AMD_COMMON_BLOCK_AOAC
+	select SOC_AMD_COMMON_BLOCK_APOB
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
-	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
+	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
+	select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE
+	select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES
+	select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN
 	select SOC_AMD_COMMON_BLOCK_I2C
 	select SOC_AMD_COMMON_BLOCK_I3C
 	select SOC_AMD_COMMON_BLOCK_IOMMU
@@ -35,8 +51,11 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_NONCAR
 	select SOC_AMD_COMMON_BLOCK_PCI
 	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+	select SOC_AMD_COMMON_BLOCK_PM
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2
+	select SOC_AMD_COMMON_BLOCK_PSP_SMI
 	select SOC_AMD_COMMON_BLOCK_PSP_SPL
+	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI
 	select SOC_AMD_COMMON_BLOCK_SMM
 	select SOC_AMD_COMMON_BLOCK_SMU
@@ -47,8 +66,15 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_UART
 	select SOC_AMD_COMMON_BLOCK_UCODE
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
+	select SOC_AMD_COMMON_BLOCK_XHCI
 	select SOC_AMD_OPENSIL
 	select OPENSIL_DRIVER
+	select DRAM_SUPPORT_DDR5
+	select SSE2
+	select X86_AMD_FIXED_MTRRS
+	select X86_INIT_NEED_1_SIPI
+	select VBOOT_X86_SHA256_ACCELERATION if VBOOT
+	select UDK_2017_BINDING
 
 config USE_X86_64_SUPPORT
 	default y
@@ -73,7 +99,11 @@ config EARLY_RESERVED_DRAM_BASE
 
 config EARLYRAM_BSP_STACK_SIZE
 	hex
-	default 0x1000
+	default 0x10000
+
+config STACK_SIZE
+	hex
+	default 0x10000
 
 config MAX_CPUS
 	int
@@ -81,14 +111,18 @@ config MAX_CPUS
 
 config PSP_APOB_DRAM_ADDRESS
 	hex
-	default 0x7001000
+	default 0x7010000
 	help
 	  Location in DRAM where the PSP will copy the AGESA PSP Output
 	  Block.
 
 config PSP_APOB_DRAM_SIZE
 	hex
-	default 0x20000
+	default 0xd0000
+
+config MRC_SETTINGS_CACHE_SIZE
+	hex
+	default 0xd0000
 
 config PRERAM_CBMEM_CONSOLE_SIZE
 	hex
@@ -106,7 +140,7 @@ config C_ENV_BOOTBLOCK_SIZE
 
 config ROMSTAGE_ADDR
 	hex
-	default 0x7050000
+	default 0x7150000
 	help
 	  Sets the address in DRAM where romstage should be loaded.
 
@@ -124,6 +158,14 @@ config ECAM_MMCONF_BUS_NUMBER
 	int
 	default 256
 
+config DISABLE_KEYBOARD_RESET_PIN
+	bool
+	help
+	  Instruct the SoC to not use the state of GPIO_129 as keyboard reset.
+
+config CPU_PT_ROM_MAP_GB
+	default 1024
+
 menu "PSP Configuration Options"
 
 config AMDFW_CONFIG_FILE
@@ -141,7 +183,7 @@ config PSP_INIT_ESPI
 	  Select to initialize the eSPI controller in the PSP Stage 2 Boot
 	  Loader.
 
-config	PSP_UNLOCK_SECURE_DEBUG
+config PSP_UNLOCK_SECURE_DEBUG
 	bool
 	default y
 
@@ -171,6 +213,11 @@ config PSP_SOFTFUSE_BITS
 	          0=SoC MMIO UART, 1=IO port 0x3F8
 
 	  See #57299 (NDA) for additional bit definitions.
+
+config PSPV2_MBOX_CMD_OFFSET
+	hex
+	default 0x10970
+
 endmenu
 
 config CONSOLE_UART_BASE_ADDRESS
@@ -179,6 +226,7 @@ config CONSOLE_UART_BASE_ADDRESS
 	default 0xfedc9000 if UART_FOR_CONSOLE = 0
 	default 0xfedca000 if UART_FOR_CONSOLE = 1
 	default 0xfedce000 if UART_FOR_CONSOLE = 2
+	default 0xfedcf000 if UART_FOR_CONSOLE = 3
 
 config SMM_TSEG_SIZE
 	hex
@@ -208,4 +256,44 @@ config ACPI_BERT_SIZE
 	  Specify the amount of DRAM reserved for gathering the data used to
 	  generate the ACPI table.
 
+config ASYNC_FILE_LOADING
+	bool "Loads files from SPI asynchronously"
+	select COOP_MULTITASKING
+	select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
+	select CBFS_PRELOAD
+	help
+	  When enabled, the platform will use the LPC SPI DMA controller to
+	  asynchronously load contents from the SPI ROM. This will improve
+	  boot time because the CPUs can be performing useful work while the
+	  SPI contents are being preloaded.
+
+config CBFS_CACHE_SIZE
+	hex
+	default 0x40000 if CBFS_PRELOAD
+
+config VBOOT
+	select VBOOT_STARTS_IN_BOOTBLOCK
+	select VBOOT_VBNV_CMOS
+	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
+
+config RO_REGION_ONLY
+	string
+	depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
+	default "apu/amdfw"
+
+config DISABLE_SPI_FLASH_ROM_SHARING
+	def_bool n
+	help
+	  Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
+	  which indicates a board level ROM transaction request. This
+	  removes arbitration with board and assumes the chipset controls
+	  the SPI flash bus entirely.
+
+config SERIRQ_CONTINUOUS_MODE
+	bool
+	default n
+	help
+	  Set this option to y for serial IRQ in continuous mode.
+	  Otherwise it is in quiet mode.
+
 endif # SOC_AMD_TURIN_POC
diff --git a/src/soc/amd/turin_poc/Makefile.mk b/src/soc/amd/turin_poc/Makefile.mk
index ab4d40f257..68144574c2 100644
--- a/src/soc/amd/turin_poc/Makefile.mk
+++ b/src/soc/amd/turin_poc/Makefile.mk
@@ -32,6 +32,7 @@ ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1)
 CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000
 endif
 
+ifneq ($(call strip_quotes, $(CONFIG_AMDFW_CONFIG_FILE)),)
 #
 # PSP Directory Table items
 #
@@ -79,6 +80,14 @@ PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf
 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 
+ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y)
+# type = 0x63 - construct APOB NV base/size from flash map
+# The flashmap section used for this is expected to be named RW_MRC_CACHE
+# Size should be 0xD0000
+APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE)
+APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START)
+endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE
+
 # Helper function to return a value with given bit set
 # Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions.
 set-bit=$(call int-shift-left, 1 $(call _toint,$1))
@@ -104,6 +113,9 @@ OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
 OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
 OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
 
+OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size)
+OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE), --apob-nv-base)
+
 OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
 OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed)
 OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
@@ -112,14 +124,22 @@ OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
 OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
 OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
 
+OPT_UCODE_FILES=$(foreach i, $(shell seq $(words $(amd_microcode_bins))), \
+	$(call add_opt_prefix, $(word $(i), $(amd_microcode_bins)), \
+	--instance $(shell printf "%x" $$(($(i)-1))) --ucode))
+
 AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
 		$(OPT_APOB_ADDR) \
+		$(OPT_APOB_NV_SIZE) \
+		$(OPT_APOB_NV_BASE) \
+		$(OPT_UCODE_FILES) \
 		$(OPT_DEBUG_AMDFWTOOL) \
 		$(OPT_PSP_BIOSBIN_FILE) \
 		$(OPT_PSP_BIOSBIN_DEST) \
 		$(OPT_PSP_BIOSBIN_SIZE) \
 		$(OPT_PSP_SOFTFUSE) \
 		--use-pspsecureos \
+		--load-s0i3 \
 		$(OPT_TOKEN_UNLOCK) \
 		$(OPT_WHITELIST_FILE) \
 		$(OPT_SPL_TABLE_FILE) \
@@ -127,11 +147,12 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
 		$(OPT_EFS_SPI_SPEED) \
 		$(OPT_EFS_SPI_MICRON_FLAG) \
 		--config $(CONFIG_AMDFW_CONFIG_FILE) \
-		--flashsize 0x1000000
+		--flashsize $(call strip_quotes, $(CONFIG_ROM_SIZE))
 
 $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 			$$(PSP_APCB_FILES) \
 			$(DEP_FILES) \
+			$(UCODE_FILES) \
 			$(AMDFWTOOL) \
 			$(obj)/fmap_config.h \
 			$(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file
@@ -157,4 +178,8 @@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
 	$(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
 		--maxsize $(PSP_BIOSBIN_SIZE)
 
+else
+# Set FIRMWARE_LOCATION to get the microcode files
+FIRMWARE_LOCATION=3rdparty/amd_firmwares/Firmwares/Turin
+endif # ifneq ($(call strip_quotes, $(CONFIG_AMDFW_CONFIG_FILE)),)
 endif
diff --git a/src/soc/amd/turin_poc/acpi.c b/src/soc/amd/turin_poc/acpi.c
index 9091050ba5..224f2464a9 100644
--- a/src/soc/amd/turin_poc/acpi.c
+++ b/src/soc/amd/turin_poc/acpi.c
@@ -6,7 +6,6 @@
 #include <amdblocks/acpi.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/cpu.h>
-#include <arch/ioapic.h>
 #include <device/device.h>
 #include <drivers/amd/opensil/opensil.h>
 
@@ -40,6 +39,7 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long c
 				    struct acpi_rsdp *rsdp)
 {
 	/* IVRS */
+	printk(BIOS_DEBUG, "ACPI:   * IVRS\n");
 	current = acpi_add_ivrs_table(current, rsdp);
 
 	return current;
@@ -54,7 +54,7 @@ const acpi_cstate_t cstate_cfg_table[] = {
 	},
 	[1] = {
 		.ctype = 2,
-		.latency = 0x12,
+		.latency = 0x64,
 		.power = 0,
 	},
 };
diff --git a/src/soc/amd/turin_poc/acpi/mmio.asl b/src/soc/amd/turin_poc/acpi/mmio.asl
index 9b5e1d2d2b..6ec247f788 100644
--- a/src/soc/amd/turin_poc/acpi/mmio.asl
+++ b/src/soc/amd/turin_poc/acpi/mmio.asl
@@ -33,6 +33,7 @@ Device (GPIO)
 				Shared, , , IRQR)
 			{ 0 }
 			Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+			Memory32Fixed (ReadWrite, ACPIMMIO_RGPIO_BASE, 0x2C)
 		}
 		CreateDWordField (Local0, IRQR._INT, IRQN)
 		If (PICM) {
@@ -43,6 +44,7 @@ Device (GPIO)
 		If (IRQN == 0x1f || IRQN == 0) {
 			Return (ResourceTemplate() {
 				Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+				Memory32Fixed (ReadWrite, ACPIMMIO_RGPIO_BASE, 0x2C)
 			})
 		} Else {
 			Return (Local0)
@@ -68,6 +70,7 @@ Device (FUR0)
 				Exclusive, , , IRQR)
 			{ 0 }
 			Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+			Memory32Fixed (ReadWrite, APU_DMA0_BASE, 0x1000)
 		}
 		CreateDWordField (Local0, IRQR._INT, IRQN)
 		If (PICM) {
@@ -78,6 +81,7 @@ Device (FUR0)
 		If (IRQN == 0x1f) {
 			Return (ResourceTemplate() {
 				Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+				Memory32Fixed (ReadWrite, APU_DMA0_BASE, 0x1000)
 			})
 		} Else {
 			Return (Local0)
@@ -105,6 +109,7 @@ Device (FUR1) {
 				Exclusive, , , IRQR)
 			{ 0 }
 			Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+			Memory32Fixed (ReadWrite, APU_DMA1_BASE, 0x1000)
 		}
 		CreateDWordField (Local0, IRQR._INT, IRQN)
 		If (PICM) {
@@ -115,6 +120,7 @@ Device (FUR1) {
 		If (IRQN == 0x1f) {
 			Return (ResourceTemplate() {
 				Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+				Memory32Fixed (ReadWrite, APU_DMA1_BASE, 0x1000)
 			})
 		} Else {
 			Return (Local0)
@@ -142,6 +148,7 @@ Device (FUR2) {
 				Exclusive, , , IRQR)
 			{ 0 }
 			Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
+			Memory32Fixed (ReadWrite, APU_DMA2_BASE, 0x1000)
 		}
 		CreateDWordField (Local0, IRQR._INT, IRQN)
 		If (PICM) {
@@ -152,6 +159,7 @@ Device (FUR2) {
 		If (IRQN == 0x1f) {
 			Return (ResourceTemplate() {
 				Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
+				Memory32Fixed (ReadWrite, APU_DMA2_BASE, 0x1000)
 			})
 		} Else {
 			Return (Local0)
@@ -167,6 +175,45 @@ Device (FUR2) {
 	AOAC_DEVICE(FCH_AOAC_DEV_UART2, 0)
 }
 
+Device (FUR3) {
+	Name (_HID, "AMDI0020")
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000)
+			Memory32Fixed (ReadWrite, APU_DMA3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IUA3
+		} Else {
+			IRQN = PUA3
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000)
+				Memory32Fixed (ReadWrite, APU_DMA3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_UART3, 0)
+}
+
 Device (I2C0) {
 	Name (_HID, "AMDI0010")
 	Name (_UID, 0x0)
@@ -412,3 +459,187 @@ Device (MISC)
 		Return (0x0B)
 	}
 }
+
+Device (I3C0)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II20
+		} Else {
+			IRQN = PI20
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0)
+}
+
+Device (I3C1)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II21
+		} Else {
+			IRQN = PI21
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0)
+}
+
+Device (I3C2)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II22
+		} Else {
+			IRQN = PI22
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0)
+}
+
+Device (I3C3)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II23
+		} Else {
+			IRQN = PI23
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0)
+}
diff --git a/src/soc/amd/turin_poc/acpi/pci_int_defs.asl b/src/soc/amd/turin_poc/acpi/pci_int_defs.asl
index 22455c5cae..14b2f7db44 100644
--- a/src/soc/amd/turin_poc/acpi/pci_int_defs.asl
+++ b/src/soc/amd/turin_poc/acpi/pci_int_defs.asl
@@ -21,17 +21,30 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	PIRG, 0x00000008,	/* Index 6: INTG */
 	PIRH, 0x00000008,	/* Index 7: INTH */
 
-	Offset (0x10),
+	Offset (0xc),
+	SIRA, 0x00000008,	/* Index 0xc: Serial IRQ A */
+	SIRB, 0x00000008,	/* Index 0xd: Serial IRQ B */
+	SIRC, 0x00000008,	/* Index 0xe: Serial IRQ C */
+	SIRD, 0x00000008,	/* Index 0xf: Serial IRQ D */
 	PSCI, 0x00000008,	/* Index 0x10: SCI */
 	PSB0, 0x00000008,	/* Index 0x11: SMBUS0 */
 	PASF, 0x00000008,	/* Index 0x12: ASF */
+	PHDA, 0x00000008,	/* Index 0x12: HDA */
 
 	Offset (0x16),
 	PPMN, 0x00000008,	/* Index 0x16: PerMon */
+	PSDC, 0x00000008,	/* Index 0x17: SD */
 
 	Offset (0x1a),
 	PSIO, 0x00000008,	/* Index 0x1A: SDIO */
 
+	Offset (0x30),
+	PUS1, 0x00000008,	/* Index 0x30: USB EMU */
+	Offset (0x34),
+	PUS3, 0x00000008,	/* Index 0x34: XHCI0 */
+	Offset (0x41),
+	PSAT, 0x00000008,	/* Index 0x41: SATA */
+
 	Offset (0x50),
 	PGP0, 0x00000008,	/* Index 0x50: GPP0 */
 	PGP1, 0x00000008,	/* Index 0x51: GPP1 */
@@ -64,27 +77,40 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	IORG, 0x00000008,	/* Index 0x86: INTG */
 	IORH, 0x00000008,	/* Index 0x87: INTH */
 
-	Offset (0x90),
+	Offset (0x8c),
+	ISIA, 0x00000008,	/* Index 0x8c: Serial IRQ A */
+	ISIB, 0x00000008,	/* Index 0x8d: Serial IRQ B */
+	ISIC, 0x00000008,	/* Index 0x8e: Serial IRQ C */
+	ISID, 0x00000008,	/* Index 0x8f: Serial IRQ D */
 	ISCI, 0x00000008,	/* Index 0x90: SCI */
 	ISB0, 0x00000008,	/* Index 0x91: SMBUS0 */
 	IASF, 0x00000008,	/* Index 0x92: ASF */
+	IHDA, 0x00000008,	/* Index 0x93: HDA */
 
 	Offset (0x96),
 	IPMN, 0x00000008,	/* Index 0x96: PerMon */
+	ISDC, 0x00000008,	/* Index 0x97: SD */
 
 	Offset (0x9a),
 	ISIO, 0x00000008,	/* Index 0x9A: SDIO */
 
-	Offset (0xD0),
+	Offset (0xb0),
+	IUS1, 0x00000008,	/* Index 0xb0: USB EMU */
+	Offset (0xb4),
+	IUS3, 0x00000008,	/* Index 0xb4: XHCI0 */
+	Offset (0xc1),
+	ISAT, 0x00000008,	/* Index 0xc1: SATA */
+
+	Offset (0xd0),
 	IGP0, 0x00000008,	/* Index 0xD0: GPP0 */
 	IGP1, 0x00000008,	/* Index 0xD1: GPP1 */
 	IGP2, 0x00000008,	/* Index 0xD2: GPP2 */
 	IGP3, 0x00000008,	/* Index 0xD3: GPP3 */
 
-	Offset (0xE2),
+	Offset (0xe2),
 	IGPI, 0x00000008,	/* Index 0xE2: GPIO */
 
-	Offset (0xF0),
+	Offset (0xf0),
 	II20, 0x00000008,	/* Index 0xF0: I2C0/I3C0 */
 	II21, 0x00000008,	/* Index 0xF1: I2C1/I3C1 */
 	II22, 0x00000008,	/* Index 0xF2: I2C2/I3C2 */
diff --git a/src/soc/amd/turin_poc/acpi/resources.asl b/src/soc/amd/turin_poc/acpi/resources.asl
new file mode 100644
index 0000000000..98437690b5
--- /dev/null
+++ b/src/soc/amd/turin_poc/acpi/resources.asl
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* PCI Device Resource Consumption */
+Device (PDRC) {
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 0x700)
+	Name (_STA, 0x0F)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0010, 0x0010, 0x00, 0x10, )
+		IO (Decode16, 0x0022, 0x0022, 0x00, 0x1e, )
+		IO (Decode16, 0x0063, 0x0063, 0x00, 0x01, )
+		IO (Decode16, 0x0065, 0x0065, 0x00, 0x01, )
+		IO (Decode16, 0x0067, 0x0067, 0x00, 0x09, )
+		IO (Decode16, 0x0072, 0x0072, 0x00, 0x0E, )
+		IO (Decode16, 0x0080, 0x0080, 0x00, 0x01, )
+		IO (Decode16, 0x0084, 0x0084, 0x00, 0x03, )
+		IO (Decode16, 0x0088, 0x0088, 0x00, 0x01, )
+		IO (Decode16, 0x008c, 0x008c, 0x00, 0x03, )
+		IO (Decode16, 0x0090, 0x0090, 0x00, 0x10, )
+		IO (Decode16, 0x00a2, 0x00a2, 0x00, 0x1e, )
+		IO (Decode16, 0x00b1, 0x00b1, 0x00, 0x01, )
+		IO (Decode16, 0x00e0, 0x00e0, 0x00, 0x10, )
+		/* ACPI */
+		IO (Decode16, 0x0400, 0x0400, 0x00, 0xa0, )
+		/* DMA */
+		IO (Decode16, 0x040b, 0x040b, 0x00, 0x01, )
+		/* INTR edge control */
+		IO (Decode16, 0x04d0, 0x04d0, 0x00, 0x02, )
+		/* DMA */
+		IO (Decode16, 0x04d6, 0x04d6, 0x00, 0x01, )
+		IO (Decode16, 0x0900, 0x0900, 0x00, 0x10, )
+		IO (Decode16, 0x0910, 0x0910, 0x00, 0x10, )
+		/* SMBUS */
+		IO (Decode16, 0x0b00, 0x0b00, 0x00, 0x10, )
+		/* SMBUS ASF */
+		IO (Decode16, 0x0b20, 0x0b20, 0x00, 0x20, )
+		/* PCI interrupt router */
+		IO (Decode16, 0x0c00, 0x0c00, 0x00, 0x02, )
+		/* PCI ERR */
+		IO (Decode16, 0x0c14, 0x0c14, 0x00, 0x01, )
+		IO (Decode16, 0x0c50, 0x0c50, 0x00, 0x02, )
+		IO (Decode16, 0x0c52, 0x0c52, 0x00, 0x01, )
+		IO (Decode16, 0x0c6c, 0x0c6c, 0x00, 0x01, )
+		/* ISA MISC */
+		IO (Decode16, 0x0c6f, 0x0c6f, 0x00, 0x01, )
+		IO (Decode16, 0x0cd0, 0x0cd0, 0x00, 0x02, )
+		/* PMIO2 */
+		IO (Decode16, 0x0cd2, 0x0cd2, 0x00, 0x02, )
+		/* BIOSRAM */
+		IO (Decode16, 0x0cd4, 0x0cd4, 0x00, 0x02, )
+		/* PMIO */
+		IO (Decode16, 0x0cd6, 0x0cd6, 0x00, 0x02, )
+		/* AB INDX */
+		IO (Decode16, 0x0cd8, 0x0cd8, 0x00, 0x08, )
+		/* ACPI PMA CNTL BLK */
+		IO (Decode16, 0xfe00, 0xfe00, 0x00, 0xff, )
+		Memory32Fixed (ReadWrite, 0xfee00000, 0x00001000, )
+		/* Remainder of remote GPIO up to GPIO0 bank */
+		Memory32Fixed (ReadWrite, 0xfed8122c, 0x000002d4, )
+		/* ACPI MMIO above GPIO banks */
+		Memory32Fixed (ReadWrite, 0xfed81a00, 0x0000e600, )
+		/* Watchdog */
+		Memory32Fixed (ReadWrite, 0xfeb00000, 0x00000010, )
+		/* ROM */
+		Memory32Fixed (ReadWrite, 0xff000000, 0x01000000, )
+	})
+}
diff --git a/src/soc/amd/turin_poc/acpi/soc.asl b/src/soc/amd/turin_poc/acpi/soc.asl
index 75344dc325..5d18024705 100644
--- a/src/soc/amd/turin_poc/acpi/soc.asl
+++ b/src/soc/amd/turin_poc/acpi/soc.asl
@@ -19,6 +19,15 @@ Scope(\_SB) {
 	ROOT_BRIDGE(S0B1)
 	ROOT_BRIDGE(S0B2)
 	ROOT_BRIDGE(S0B3)
+	ROOT_BRIDGE(S0B4)
+	ROOT_BRIDGE(S0B5)
+	ROOT_BRIDGE(S0B6)
+	ROOT_BRIDGE(S0B7)
+
+	Scope(S0B0) {
+		#include "resources.asl"
+		#include <soc/amd/common/acpi/lpc.asl>
+	} /* End S0B0 scope */
 } /* End \_SB scope */
 
 #include <soc/amd/common/acpi/alib.asl>
@@ -34,6 +43,4 @@ Scope(\_SB) {
  */
 Method (PNOT)
 {
-	/* Report AC/DC state to ALIB using WAL1() */
-	\WAL1 ()
 }
diff --git a/src/soc/amd/turin_poc/chip.c b/src/soc/amd/turin_poc/chip.c
index 344617d52e..ee5ad5e0a0 100644
--- a/src/soc/amd/turin_poc/chip.c
+++ b/src/soc/amd/turin_poc/chip.c
@@ -2,6 +2,7 @@
 
 #include <amdblocks/acpi.h>
 #include <amdblocks/data_fabric.h>
+#include <cpu/x86/mtrr.h>
 #include <device/device.h>
 #include <drivers/amd/opensil/opensil.h>
 #include <soc/southbridge.h>
@@ -10,6 +11,8 @@ static void soc_init(void *chip_info)
 {
 	default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
 
+	display_mtrrs();
+
 	amd_opensil_silicon_init();
 
 	data_fabric_print_mmio_conf();
diff --git a/src/soc/amd/turin_poc/chip.h b/src/soc/amd/turin_poc/chip.h
index f08f348f15..1bfe6e6c92 100644
--- a/src/soc/amd/turin_poc/chip.h
+++ b/src/soc/amd/turin_poc/chip.h
@@ -9,6 +9,11 @@
 #include <soc/iomap.h>
 #include <types.h>
 
+#define MAX_DOMAINS	8
+
+static const unsigned int domain_to_rb_index[MAX_DOMAINS] = { 2, 7, 3, 6, 4, 1, 5, 0 };
+static const unsigned int domain_to_logical_rb[MAX_DOMAINS] = { 4, 5, 6, 7, 3, 2, 1, 0 };
+
 struct usb31_phy_settings {
 	uint8_t rx_ana_iq_phase_adjust;
 	uint8_t rx_eq_delta_iq_ovrd_en;
@@ -30,33 +35,23 @@ struct soc_usb_config {
 	struct {
 		uint8_t port0 : 4;
 		uint8_t port1 : 4;
-		uint8_t port2 : 4;
-		uint8_t port3 : 4;
-		uint8_t port4 : 4;
-		uint8_t port5 : 4;
-		uint8_t port6 : 4;
-		uint8_t port7 : 4;
 	} usb2_oc_pins[2];
 	struct {
 		uint8_t port0 : 4;
 		uint8_t port1 : 4;
-		uint8_t port2 : 4;
-		uint8_t port3 : 4;
 	}  usb3_oc_pins[2];
 	bool polarity_cfg_low;
 	union {
 		struct {
 			uint8_t port0 : 2;
 			uint8_t port1 : 2;
-			uint8_t port2 : 2; /* Broken in OpenSIL */
-			uint8_t port3 : 2; /* Broken in OpenSIL */
 		};
 		uint8_t raw;
 	} usb3_force_gen1;
 	bool usb31_phy_enable;
-	struct usb31_phy_settings usb31_phy[8];
+	struct usb31_phy_settings usb31_phy[2];
 	bool s1_usb31_phy_enable;
-	struct usb31_phy_settings s1_usb31_phy[8];
+	struct usb31_phy_settings s1_usb31_phy[2];
 };
 
 struct soc_amd_turin_poc_config {
diff --git a/src/soc/amd/turin_poc/chipset.cb b/src/soc/amd/turin_poc/chipset.cb
index 399d3530fc..f8f4888658 100644
--- a/src/soc/amd/turin_poc/chipset.cb
+++ b/src/soc/amd/turin_poc/chipset.cb
@@ -4,14 +4,14 @@ chip soc/amd/turin_poc
 	device cpu_cluster 0 on ops amd_cpu_bus_ops end
 
 	# OC pins
-	register "usb.usb2_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
-	register "usb.usb2_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
-	register "usb.usb3_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf }"
-	register "usb.usb3_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf }"
+	register "usb.usb2_oc_pins[0]" = "{ 0xf, 0xf }"
+	register "usb.usb2_oc_pins[1]" = "{ 0xf, 0xf }"
+	register "usb.usb3_oc_pins[0]" = "{ 0xf, 0xf }"
+	register "usb.usb3_oc_pins[1]" = "{ 0xf, 0xf }"
 
 	device domain 0 on
 		ops turin_pci_domain_ops
-		device pci 00.0 alias gnb_0 on end
+		device pci 00.0 alias gnb_0 on ops turin_root_complex_operations end
 		device pci 00.2 alias iommu_0 off ops amd_iommu_ops end
 		device pci 00.3 alias rcec_0 off end
 
@@ -47,69 +47,19 @@ chip soc/amd/turin_poc
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 03.1 alias gpp_bridge_0_0_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.2 alias gpp_bridge_0_1_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.3 alias gpp_bridge_0_2_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.4 alias gpp_bridge_0_3_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.5 alias gpp_bridge_0_4_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.6 alias gpp_bridge_0_5_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.7 alias gpp_bridge_0_6_b off end
-		end
-
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 04.1 alias gpp_bridge_0_7_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 04.2 alias gpp_bridge_0_8_b off end
-		end
-
 		device pci 05.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 05.1 alias gpp_bridge_0_0_c off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 05.2 alias gpp_bridge_0_1_c off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 05.3 alias gpp_bridge_0_2_c off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 05.4 alias gpp_bridge_0_3_c off end
-		end
 
 		device pci 07.0 on end # Dummy device function, do not disable
-		device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0
-			device pci 0.0 on end # Dummy PCIe function
-			device pci 0.1 off end
-			device pci 0.2 alias primary_NTB_0 off end # Primary PCIe Non-TransparentBridge
-			device pci 0.3 alias secondry_NTB_0 off end # Secondary vNTB
-			device pci 0.4 alias xhci_0 off end # USB
-			device pci 0.5 alias mp0_0 off end # PSP (MP0)
-			device pci 0.6 alias acp_0 off end # Audio Processor (ACP)
-			device pci 0.7 alias hda_0 off end # Audio Processor HD Audio Controller (main AZ)
-		end
-		device pci 07.2 alias gpp_bridge_0_b off # Internal GPP Bridge 1 to Bus C0
-			device pci 0.0 alias sata_0_0 off end # first SATA controller; AHCI mode
-			device pci 0.1 alias sata_0_1 off end # second SATA controller; AHCI mode
+		device pci 07.1 alias gpp_bridge_0_a on # Internal GPP Bridge 0 to Bus C0
+			device pci 00.0 alias nbif_0 on end # Dummy PCIe function
+			device pci 00.1 alias sdxi_1 on end # Smart Data Accelerator Interface
+			device pci 00.2 alias primary_NTB_1 off end # Primary PCIe Non-TransparentBridge
+			device pci 00.3 alias secondry_NTB_1 off end # Secondary vNTB
 		end
 
 		device pci 14.0 alias smbus on end # primary FCH function
 		device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end
-		device pci 14.6 alias sdhci off end
 
 		device pci 18.0 alias data_fabric_0 on end
 		device pci 18.1 alias data_fabric_1 on end
@@ -123,8 +73,7 @@ chip soc/amd/turin_poc
 
 	device domain 1 on
 		ops turin_pci_domain_ops
-		device pci 00.0 alias gnb_1 on end
-		device pci 00.2 alias iommu_1 off ops amd_iommu_ops end
+		device pci 00.0 alias gnb_1 on ops turin_root_complex_operations  end
 		device pci 00.3 alias rcec_1 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
@@ -157,54 +106,12 @@ chip soc/amd/turin_poc
 		chip drivers/amd/opensil/mpio
 			device pci 02.2 alias gpp_bridge_1_8_a off end
 		end
-
-		device pci 03.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 03.1 alias gpp_bridge_1_0_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.2 alias gpp_bridge_1_1_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.3 alias gpp_bridge_1_2_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.4 alias gpp_bridge_1_3_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.5 alias gpp_bridge_1_4_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.6 alias gpp_bridge_1_5_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.7 alias gpp_bridge_1_6_b off end
-		end
-
-		device pci 04.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 04.1 alias gpp_bridge_1_7_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 04.2 alias gpp_bridge_1_8_b off end
-		end
-
-		device pci 05.0 on end # Dummy device function, do not disable
-
-		device pci 07.0 on end # Dummy device function, do not disable
-		device pci 07.1 alias gpp_bridge_1_a off
-			device pci 0.0 on end # Dummy PCIe function
-			device pci 0.1 off end #SDXI
-			device pci 0.2 alias primary_NTB_1 off end # Primary PCIe Non-TransparentBridge
-			device pci 0.3 alias secondry_NTB_1 off end # Secondary vNTB
-		end
 	end
 
 	device domain 2 on
 		ops turin_pci_domain_ops
-		device pci 00.0 alias gnb_2 on end
+		device pci 00.0 alias gnb_2 on ops turin_root_complex_operations end
 		device pci 00.2 alias iommu_2 off ops amd_iommu_ops end
-		device pci 00.3 alias rcec_2 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
 		chip drivers/amd/opensil/mpio
@@ -238,52 +145,36 @@ chip soc/amd/turin_poc
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 03.1 alias gpp_bridge_2_0_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.2 alias gpp_bridge_2_1_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.3 alias gpp_bridge_2_2_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.4 alias gpp_bridge_2_3_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.5 alias gpp_bridge_2_4_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.6 alias gpp_bridge_2_5_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.7 alias gpp_bridge_2_6_b off end
-		end
-
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 04.1 alias gpp_bridge_2_7_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 04.2 alias gpp_bridge_2_8_b off end
-		end
 
 		device pci 05.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 05.1 alias gpp_bridge_2_0_c off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 05.2 alias gpp_bridge_2_1_c off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 05.3 alias gpp_bridge_2_2_c off end
+		end
 
 		device pci 07.0 on end # Dummy device function, do not disable
-		device pci 07.1 alias gpp_bridge_2_a off
-			device pci 0.0 on end # Dummy PCIe function
-			device pci 0.1 off end
-			device pci 0.2 alias primary_NTB_2 off end # Primary PCIe Non-TransparentBridge
-			device pci 0.3 alias secondry_NTB_2 off end # Secondary vNTB
+		device pci 07.1 alias gpp_bridge_2_a on # Internal GPP Bridge 0 to Bus C1
+			device pci 00.0 alias nbif_2 on end # Dummy PCIe function
+			device pci 00.1 alias sdxi_2 on end # Smart Data Accelerator Interface
+			device pci 00.3 alias secondry_NTB_2 off end # Secondary vNTB
+			device pci 00.4 alias xhci_0 off end # USB
+			device pci 00.7 alias hda off end # HD Audio Controller (AZ)
+		end
+		device pci 07.2 alias gpp_bridge_2_b on # Internal GPP Bridge 0 to Bus D1
+			device pci 00.0 alias sata_2_0 off end # first SATA controller; AHCI mode
+			device pci 00.1 alias sata_2_1 off end # second SATA controller; AHCI mode
 		end
 	end
 
 	device domain 3 on
 		ops turin_pci_domain_ops
-		device pci 00.0 alias gnb_3 on end
-		device pci 00.2 alias iommu_3 off ops amd_iommu_ops end
-		device pci 00.3 alias rcec_3 off end
+		device pci 00.0 alias gnb_3 on ops turin_root_complex_operations end
 
 		device pci 01.0 on end # Dummy device function, do not disable
 		chip drivers/amd/opensil/mpio
@@ -315,66 +206,221 @@ chip soc/amd/turin_poc
 		chip drivers/amd/opensil/mpio
 			device pci 02.2 alias gpp_bridge_3_8_a off end
 		end
+	end
+
+	device domain 4 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_4 on ops turin_root_complex_operations end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_4_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_4_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_4_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_4_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_4_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_4_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_4_6_a off end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_4_7_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_4_8_a off end
+		end
+	end
+
+	device domain 5 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_5 on ops turin_root_complex_operations end
+		device pci 00.2 alias iommu_5 off ops amd_iommu_ops end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_5_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_5_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_5_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_5_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_5_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_5_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_5_6_a off end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_5_7_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_5_8_a off end
+		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
 		chip drivers/amd/opensil/mpio
-			device pci 03.1 alias gpp_bridge_3_0_b off end
+			device pci 03.1 alias gpp_bridge_5_0_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.2 alias gpp_bridge_3_1_b off end
+			device pci 03.2 alias gpp_bridge_5_1_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.3 alias gpp_bridge_3_2_b off end
+			device pci 03.3 alias gpp_bridge_5_2_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.4 alias gpp_bridge_3_3_b off end
+			device pci 03.4 alias gpp_bridge_5_3_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.5 alias gpp_bridge_3_4_b off end
+			device pci 03.5 alias gpp_bridge_5_4_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.6 alias gpp_bridge_3_5_b off end
+			device pci 03.6 alias gpp_bridge_5_5_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.7 alias gpp_bridge_3_6_b off end
+			device pci 03.7 alias gpp_bridge_5_6_b off end
 		end
 
 		device pci 04.0 on end # Dummy device function, do not disable
 		chip drivers/amd/opensil/mpio
-			device pci 04.1 alias gpp_bridge_3_7_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 04.2 alias gpp_bridge_3_8_b off end
+			device pci 04.1 alias gpp_bridge_5_7_b off end
 		end
 
 		device pci 05.0 on end # Dummy device function, do not disable
 		chip drivers/amd/opensil/mpio
-			device pci 05.1 alias gpp_bridge_3_0_c off end
+			device pci 05.1 alias gpp_bridge_5_0_c off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 05.2 alias gpp_bridge_3_1_c off end
+			device pci 05.2 alias gpp_bridge_5_1_c off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 05.3 alias gpp_bridge_3_2_c off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 05.4 alias gpp_bridge_3_3_c off end
+			device pci 05.3 alias gpp_bridge_5_2_c off end
 		end
 
 		device pci 07.0 on end # Dummy device function, do not disable
-		device pci 07.1 alias gpp_bridge_3_a off
-			device pci 0.0 on end # Dummy PCIe function
-			device pci 0.1 off end #SDXI
-			device pci 0.2 alias primary_NTB_3 off end # Primary PCIe Non-TransparentBridge
-			device pci 0.3 alias secondry_NTB_3 off end # Secondary vNTB
-			device pci 0.4 alias xhci_3 off end # USB
-			device pci 0.5 alias mp0_3 off end # PSP (MP0)
+		device pci 07.1 alias gpp_bridge_3_a on # Internal GPP Bridge 0 to Bus C2
+			device pci 00.0 alias nbif_3 on end # Dummy PCIe function
+			device pci 00.1 alias sdxi_3 on end # Smart Data Accelerator Interface
+			device pci 00.2 alias primary_NTB_3 off end # Primary PCIe Non-TransparentBridge
+			device pci 00.3 alias secondry_NTB_3 off end # Secondary vNTB
+			device pci 00.5 alias asp off end # PSP (MP0)
+		end
+	end
+
+	device domain 6 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_6 on ops turin_root_complex_operations end
+		device pci 00.3 alias rcec_6 off end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_6_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_6_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_6_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_6_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_6_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_6_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_6_6_a off end
 		end
 
-		device pci 07.2 alias gpp_bridge_3_b off
-			device pci 0.0 alias sata_3_0 off end # first SATA controller; AHCI mode
-			device pci 0.1 alias sata_3_1 off end # second SATA controller; AHCI mode
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_6_7_a off end
 		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_6_8_a off end
+		end
+	end
+
+	device domain 7 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_7 on ops turin_root_complex_operations end
+		device pci 00.2 alias iommu_7 off ops amd_iommu_ops end
+		device pci 00.3 alias rcec_7 off end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_7_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_7_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_7_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_7_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_7_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_7_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_7_6_a off end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_7_7_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_7_8_a off end
+		end
+
+		device pci 03.0 on end # Dummy device function, do not disable
+		device pci 04.0 on end # Dummy device function, do not disable
+		device pci 05.0 on end # Dummy device function, do not disable
+
+		device pci 07.0 on end # Dummy device function, do not disable
+		device pci 07.1 alias gpp_bridge_7_a on # Internal GPP Bridge 0 to Bus C3
+			device pci 00.0 alias nbif_4 on end # Dummy PCIe function
+			device pci 00.1 alias sdxi_4 on end # Smart Data Accelerator Interface
+			device pci 00.2 alias primary_NTB_4 off end # Primary PCIe Non-TransparentBridge
+			device pci 00.3 alias secondry_NTB_4 off end # Secondary vNTB
+			device pci 00.4 alias xhci_1 off end # USB
+		end
+
+		device pci 07.2 alias gpp_bridge_7_b on # Internal GPP Bridge 0 to Bus D3
+			device pci 00.0 alias sata_7_0 off end # first SATA controller; AHCI mode
+			device pci 00.1 alias sata_7_1 off end # second SATA controller; AHCI mode
+		end
+
 	end
 
 	device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
diff --git a/src/soc/amd/turin_poc/cpu.c b/src/soc/amd/turin_poc/cpu.c
index aedd0ac6cf..fc1ad627eb 100644
--- a/src/soc/amd/turin_poc/cpu.c
+++ b/src/soc/amd/turin_poc/cpu.c
@@ -10,8 +10,9 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, TURIN_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
-	{ X86_VENDOR_AMD, TURIN_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, TURIN_Ax_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, TURIN_Bx_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, TURIN_Cx_CPUID, CPUID_ALL_STEPPINGS_MASK },
 	CPU_TABLE_END
 };
 
diff --git a/src/soc/amd/turin_poc/domain.c b/src/soc/amd/turin_poc/domain.c
index 40177d7dcc..6991fdc527 100644
--- a/src/soc/amd/turin_poc/domain.c
+++ b/src/soc/amd/turin_poc/domain.c
@@ -1,23 +1,56 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpigen_pci.h>
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/ioapic.h>
 #include <amdblocks/data_fabric.h>
+#include <amdblocks/iomap.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <amdblocks/smn.h>
 #include <arch/ioapic.h>
 #include <console/console.h>
+#include <cpu/cpu.h>
 #include <device/device.h>
 #include <drivers/amd/opensil/opensil.h>
+#include <soc/iomap.h>
 #include <types.h>
 
 #define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
 
+/*
+ * 12GiB of DF reserved space at the top of physical address space. The
+ * address is not fixed and depends on SME state, because it can reduce the
+ * available physical address space.
+ */
+#define DATA_FABRIC_RESERVED_BASE \
+	(POWER_OF_2(cpu_phys_address_size()) - DF_RESERVED_TOP_12GB_MMIO_SIZE)
+#define DATA_FABRIC_RESERVED_SIZE	DF_RESERVED_TOP_12GB_MMIO_SIZE
+
+/*
+ * 64KiB of ACPI EINJ buffer, reserve it. Reads return FFs and cause errors in
+ * memtest86 if not reserved, and needless to say, crashes in operating
+ * systems too.
+ */
+#define ACPI_EINJ_RESERVED_BASE		(4ull * GiB)
+#define ACPI_EINJ_RESERVED_SIZE		(64 * KiB)
+
 void read_soc_memmap_resources(struct device *domain, unsigned long *idx)
 {
 	read_lower_soc_memmap_resources(domain, idx);
 
+	if (is_domain0(domain)) {
+		reserved_ram_range(domain, (*idx)++, ACPI_EINJ_RESERVED_BASE,
+						     ACPI_EINJ_RESERVED_SIZE);
+
+		mmio_range(domain, (*idx)++, IOMMU_RESERVED_MMIO_BASE, 12ULL * GiB);
+		mmio_range(domain, (*idx)++, DATA_FABRIC_RESERVED_BASE,
+					     DATA_FABRIC_RESERVED_SIZE);
+
+		mmio_range(domain, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+		mmio_range(domain, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+	}
+
 	amd_opensil_add_memmap(domain, idx);
 }
 
@@ -48,11 +81,15 @@ static void turin_domain_set_resources(struct device *domain)
 static const char *turin_domain_acpi_name(const struct device *domain)
 {
 	const unsigned int domain_id = dev_get_domain_id(domain);
-	const char *domain_acpi_names[4] = {
+	const char *domain_acpi_names[8] = {
 		"S0B0",
 		"S0B1",
 		"S0B2",
 		"S0B3",
+		"S0B4",
+		"S0B5",
+		"S0B6",
+		"S0B7",
 	};
 
 	if (domain_id < ARRAY_SIZE(domain_acpi_names))
diff --git a/src/soc/amd/turin_poc/early_fch.c b/src/soc/amd/turin_poc/early_fch.c
index d82ebcbcf8..5bcbca0834 100644
--- a/src/soc/amd/turin_poc/early_fch.c
+++ b/src/soc/amd/turin_poc/early_fch.c
@@ -1,19 +1,73 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#define __SIMPLE_DEVICE__
+
 #include <amdblocks/espi.h>
 #include <amdblocks/lpc.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/aoac.h>
+#include <amdblocks/i2c.h>
 #include <amdblocks/pmlib.h>
+#include <amdblocks/smbus.h>
+#include <amdblocks/smn.h>
+#include <amdblocks/spi.h>
 #include <amdblocks/uart.h>
+#include <device/pci.h>
 #include <soc/southbridge.h>
 #include <soc/uart.h>
+#include <soc/i2c.h>
+
+#define SMN_D18F0_BASE		0x49000000
+
+static void df_set_pci_mmconf(void)
+{
+	uint32_t reg;
+	uint64_t mmconf_base = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
+	uint64_t mmconf_limit = mmconf_base + CONFIG_ECAM_MMCONF_LENGTH;
+
+	mmconf_limit--;
+	mmconf_limit &= 0xfff00000; /* Address bits [19:0] are fixed to be FFFFF */
+	mmconf_base |= 1; /* Range enable */
+
+	/*
+	 * We have to use I/O PCI access to SMN index/data, because MMCONF
+	 * will not work with our MMCONF address until this function returns.
+	 */
+	reg = smn_io_read32(SMN_D18F0_BASE + 0xc10);
+	reg &= ~1; /* Disable MMCONF range first */
+	smn_io_write32(SMN_D18F0_BASE + 0xc10, reg);
+
+	/* Now repeat the order in which ABL configured the MMCONF */
+	reg = mmconf_limit >> 32;
+	smn_io_write32(SMN_D18F0_BASE + 0xc1c, reg);
+	reg = mmconf_limit & 0xffffffff;
+	smn_io_write32(SMN_D18F0_BASE + 0xc18, reg);
+	reg = mmconf_base >> 32;
+	smn_io_write32(SMN_D18F0_BASE + 0xc14, reg);
+	reg = mmconf_base & 0xffffffff;
+	smn_io_write32(SMN_D18F0_BASE + 0xc10, reg);
+}
 
 /* Before console init */
 void fch_pre_init(void)
 {
+	/*
+	 * Before we can proceed with any initialization that touches PCI, we
+	 * have to ensure our PCI MMCONF base matches the register in DF.
+	 */
+	df_set_pci_mmconf();
+	/*
+	 * Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is
+	 * needed to access the GPIO registers.
+	 */
+	enable_acpimmio_decode_pm04();
+	/* Setup SPI base by calling lpc_early_init before setting up eSPI. */
+	lpc_early_init();
+	fch_spi_early_init();
+	fch_smbus_init();
 	fch_enable_cf9_io();
-
+	fch_enable_legacy_io();
+	fch_disable_legacy_dma_io();
 	enable_aoac_devices();
 	/*
 	 * On reset Range_0 defaults to enabled. We want to start with a clean
@@ -24,10 +78,29 @@ void fch_pre_init(void)
 	if (CONFIG(AMD_SOC_CONSOLE_UART))
 		set_uart_config(CONFIG_UART_FOR_CONSOLE);
 
-	configure_espi_with_mb_hook();
+	/* disable the keyboard reset function before mainboard GPIO setup */
+	if (CONFIG(DISABLE_KEYBOARD_RESET_PIN))
+		fch_disable_kb_rst();
+
+	/*
+	 * Skip eSPI configuration. The EFS/PSP DIR already contains eSPI configuration
+	 * so x86 does not need to configure it. Running configure_espi_with_mb_hook
+	 * and resetting eSPI causes the slave/AST2600 to stop printing output on serial
+	 * port. Boards may still configure I/O decodes early, if needed.
+	 *
+	 * configure_espi_with_mb_hook();
+	 */
 }
 
 /* After console init */
 void fch_early_init(void)
 {
+	reset_i2c_peripherals();
+	pm_set_power_failure_state();
+	fch_print_pmxc0_status();
+	i2c_soc_early_init();
+	show_spi_speeds_and_modes();
+
+	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
+		lpc_disable_spi_rom_sharing();
 }
diff --git a/src/soc/amd/turin_poc/fch.c b/src/soc/amd/turin_poc/fch.c
index 46f97db8ea..a55abf2718 100644
--- a/src/soc/amd/turin_poc/fch.c
+++ b/src/soc/amd/turin_poc/fch.c
@@ -37,8 +37,23 @@ static const struct irq_idx_name irq_association[] = {
 	{ PIRQ_SCI,	"SCI" },
 	{ PIRQ_SMBUS,	"SMBUS" },
 	{ PIRQ_ASF,	"ASF" },
+	{ PIRQ_HDA,	"HDA" },
+	{ PIRQ_GBE0,	"GBE0" },
+	{ PIRQ_GBE1,	"GBE1" },
 	{ PIRQ_PMON,	"PerMon" },
+	{ PIRQ_SD,	"SD" },
 	{ PIRQ_SDIO,	"SDIO" },
+	{ PIRQ_CIR,	"CIR" },
+	{ PIRQ_GPIOA,	"GPIOa" },
+	{ PIRQ_GPIOB,	"GPIOb" },
+	{ PIRQ_GPIOC,	"GPIOc" },
+	{ PIRQ_USB_EMU,	"USB_EMU" },
+	{ PIRQ_USB_DR0,	"USB_DR0" },
+	{ PIRQ_USB_DR1,	"USB_DR1" },
+	{ PIRQ_XHCI0,	"XHCI0" },
+	{ PIRQ_SSIC,	"USB_SSIC" },
+	{ PIRQ_SATA,	"SATA" },
+	{ PIRQ_UFS,	"UFS" },
 	{ PIRQ_GPP0,	"GPP0" },
 	{ PIRQ_GPP1,	"GPP1" },
 	{ PIRQ_GPP2,	"GPP2" },
@@ -64,23 +79,62 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
 	return irq_association;
 }
 
-static void set_pci_irqs(void)
-{
-	/* Write PCI_INTR regs 0xC00/0xC01 */
-	write_pci_int_table();
-
-	/* TODO: PIRQ configuration */
-}
-
 static void fch_init_acpi_ports(void)
 {
-	/* Configure and enable APMC SMI Command Port */
-	pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
-	configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
+	uint32_t reg32;
+	uint8_t reg8;
+
+	if (CONFIG(HAVE_SMI_HANDLER)) {
+		/* Configure and enable APMC SMI Command Port */
+		pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
+		configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
+
+		/* SMI on SlpTyp requires sending SMI before completion
+		  response of the I/O write. */
+		reg32 = pm_read32(PM_PCI_CTRL);
+		reg32 |= FORCE_SLPSTATE_RETRY;
+		/* Ths bit should be cleared in case of SlpType SMI trapping */
+		reg32 &= ~FORCE_STPCLK_RETRY;
+		pm_write32(PM_PCI_CTRL, reg32);
+
+		/* Disable SlpTyp feature */
+		reg8 = pm_read8(PM_RST_CTRL1);
+		reg8 &= ~SLPTYPE_CONTROL_EN;
+		pm_write8(PM_RST_CTRL1, reg8);
+
+		configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
+	} else {
+		pm_write16(PM_ACPI_SMI_CMD, 0);
+	}
+
+	/* Decode ACPI registers and enable standard features */
+	pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
+				PM_ACPI_GLOBAL_EN |
+				PM_ACPI_RTC_EN_EN |
+				PM_ACPI_TIMER_EN_EN);
+}
+
+static void fch_clk_output_48Mhz(void)
+{
+	uint32_t ctrl = misc_read32(MISC_CLK_CNTL0);
+	/* Enable BP_X48M0 Clock Output */
+	ctrl |= BP_X48M0_OUTPUT_EN;
+	misc_write32(MISC_CLK_CNTL0, ctrl);
+}
+
+static void fch_pci_int_vw_mode(void)
+{
+	pm_write32(0xa8, 0x80ffcef8);
 }
 
 void fch_init(void *chip_info)
 {
-	set_pci_irqs();
 	fch_init_acpi_ports();
+	fch_clk_output_48Mhz();
+
+	/* Write PCI_INTR regs 0xC00/0xC01 */
+	write_pci_int_table();
+	fch_pci_int_vw_mode();
+
+	fch_enable_ioapic_decode();
 }
diff --git a/src/soc/amd/turin_poc/gpio.c b/src/soc/amd/turin_poc/gpio.c
index c38719bf3f..72d0b2b0a4 100644
--- a/src/soc/amd/turin_poc/gpio.c
+++ b/src/soc/amd/turin_poc/gpio.c
@@ -20,6 +20,7 @@ static const struct soc_amd_event gpio_event_table[] = {
 	{ GPIO_23, GEVENT_16 },
 	{ GPIO_24, GEVENT_14 },
 	{ GPIO_26, GEVENT_15 },
+	{ GPIO_28, GEVENT_18 },
 	{ GPIO_76, GEVENT_11 },
 	{ GPIO_86, GEVENT_9 },
 	{ GPIO_89, GEVENT_0 },
diff --git a/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h b/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
index f093247735..82915109a7 100644
--- a/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
@@ -28,11 +28,29 @@
 #define PIRQ_SCI	0x10	/* SCI IRQ */
 #define PIRQ_SMBUS	0x11	/* SMBUS0 */
 #define PIRQ_ASF	0x12	/* ASF */
-/* 0x13-0x15 reserved */
+#define PIRQ_HDA	0x13	/* HDA */
+#define PIRQ_GBE0	0x14	/* GBE0 */
+#define PIRQ_GBE1	0x15	/* GBE1 */
 #define PIRQ_PMON	0x16	/* Performance Monitor */
-/* 0x17-0x19 reserved */
+#define PIRQ_SD		0x17	/* SD */
+/* 0x18-0x19 reserved */
 #define PIRQ_SDIO	0x1a	/* SDIO */
-/* 0x1b-0x49 reserved */
+/* 0x1b-0x1f reserved */
+#define PIRQ_CIR	0x20	/* CIR */
+#define PIRQ_GPIOA	0x21	/* GPIOa */
+#define PIRQ_GPIOB	0x22	/* GPIOb */
+#define PIRQ_GPIOC	0x23	/* GPIOc */
+/* 0x24-0x2f reserved */
+#define PIRQ_USB_EMU	0x30	/* USB Emulation */
+#define PIRQ_USB_DR0	0x31	/* USB Dual Role 1 */
+#define PIRQ_USB_DR1	0x32	/* USB Dual Role 2 */
+/* 0x33 reserved */
+#define PIRQ_XHCI0	0x34	/* XHCI0 */
+#define PIRQ_SSIC	0x35	/* USB SSIC */
+/* 0x36-0x40 reserved */
+#define PIRQ_SATA	0x41	/* SATA */
+#define PIRQ_UFS	0x42	/* UFS */
+/* 0x43-0x4f reserved */
 #define PIRQ_GPP0	0x50	/* GPPInt0 */
 #define PIRQ_GPP1	0x51	/* GPPInt1 */
 #define PIRQ_GPP2	0x52	/* GPPInt2 */
diff --git a/src/soc/amd/turin_poc/include/soc/aoac_defs.h b/src/soc/amd/turin_poc/include/soc/aoac_defs.h
index 156ee34962..2ee168ca59 100644
--- a/src/soc/amd/turin_poc/include/soc/aoac_defs.h
+++ b/src/soc/amd/turin_poc/include/soc/aoac_defs.h
@@ -18,7 +18,13 @@
 #define FCH_AOAC_DEV_I3C3		15
 #define FCH_AOAC_DEV_UART2		16
 #define FCH_AOAC_DEV_AMBA		17
+/* Bits 18-19 reserved */
+#define FCH_AOAC_DEV_UART4		20
 #define FCH_AOAC_DEV_I3C0		21
-#define FCH_AOAC_DEV_ESPI		27
+#define FCH_AOAC_DEV_ESPI1		22
+/* Bits 23-25 reserved */
+#define FCH_AOAC_DEV_UART3		26
+#define FCH_AOAC_DEV_ESPI		27 /* RO */
+#define FCH_AOAC_DEV_CPU		31
 
 #endif /* AMD_TURIN_POC_AOAC_DEFS_H */
diff --git a/src/soc/amd/turin_poc/include/soc/cpu.h b/src/soc/amd/turin_poc/include/soc/cpu.h
index eada9233fa..618ecf81d6 100644
--- a/src/soc/amd/turin_poc/include/soc/cpu.h
+++ b/src/soc/amd/turin_poc/include/soc/cpu.h
@@ -3,7 +3,8 @@
 #ifndef AMD_TURIN_POC_CPU_H
 #define AMD_TURIN_POC_CPU_H
 
-#define TURIN_A0_CPUID		CPUID_FROM_FMS(0x19, 0x10, 0)
-#define TURIN_B0_CPUID		CPUID_FROM_FMS(0x19, 0x11, 0)
+#define TURIN_Ax_CPUID		CPUID_FROM_FMS(0x1a, 0x0, 0)
+#define TURIN_Bx_CPUID		CPUID_FROM_FMS(0x1a, 0x1, 0)
+#define TURIN_Cx_CPUID		CPUID_FROM_FMS(0x1a, 0x2, 0)
 
 #endif /* AMD_TURIN_POC_CPU_H */
diff --git a/src/soc/amd/turin_poc/include/soc/data_fabric.h b/src/soc/amd/turin_poc/include/soc/data_fabric.h
index 503dc39afb..590ada3660 100644
--- a/src/soc/amd/turin_poc/include/soc/data_fabric.h
+++ b/src/soc/amd/turin_poc/include/soc/data_fabric.h
@@ -23,7 +23,7 @@ union df_vga_en {
 #define DF_PCI_CFG_BASE0		DF_REG_ID(0, 0xc80)
 #define DF_PCI_CFG_LIMIT0		DF_REG_ID(0, 0xc84)
 
-#define DF_PCI_CFG_MAP_COUNT		8
+#define DF_PCI_CFG_MAP_COUNT		16
 
 #define DF_PCI_CFG_REG_OFFSET(instance)	((instance) * 2 * sizeof(uint32_t))
 #define DF_PCI_CFG_BASE(reg)		(DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg))
@@ -54,7 +54,7 @@ union df_pci_cfg_limit {
 #define DF_IO_BASE0			DF_REG_ID(0, 0xd00)
 #define DF_IO_LIMIT0			DF_REG_ID(0, 0xd04)
 
-#define DF_IO_REG_COUNT			8
+#define DF_IO_REG_COUNT			16
 
 #define DF_IO_REG_OFFSET(instance)	((instance) * 2 * sizeof(uint32_t))
 #define DF_IO_BASE(reg)			(DF_IO_BASE0 + DF_IO_REG_OFFSET(reg))
@@ -93,13 +93,13 @@ union df_io_limit {
 #define   DF_MMIO_EXT_ADDR_SHIFT	48
 
 #define DF_MMIO_REG_SET_SIZE		4
-#define DF_MMIO_REG_SET_COUNT		16
+#define DF_MMIO_REG_SET_COUNT		32
 
 union df_mmio_control {
 	struct {
 		uint32_t re		:  1; /* [ 0.. 0] */
 		uint32_t we		:  1; /* [ 1.. 1] */
-		uint32_t		:  1; /* [ 2.. 2] */
+		uint32_t cpu_dis	:  1; /* [ 2.. 2] */
 		uint32_t np		:  1; /* [ 3.. 3] */
 		uint32_t		: 12; /* [ 4..15] */
 		uint32_t dst_fabric_id	: 12; /* [16..27] */
@@ -124,13 +124,13 @@ union df_mmio_addr_ext {
 
 union df_ficaa {
 	struct {
-		uint32_t cfg_inst_acc_en :  1; /* [ 0.. 0] */
-		uint32_t reg_num         : 10; /* [10.. 1] */
-		uint32_t func_num        :  3; /* [13..11] */
-		uint32_t b64_en          :  1; /* [14..14] */
-		uint32_t                 :  1; /* [15..15] */
-		uint32_t inst_id         :  8; /* [23..16] */
-		uint32_t                 :  8; /* [31..24] */
+		uint32_t cfg_inst_acc_en	:  1; /* [ 0.. 0] */
+		uint32_t reg_num		: 10; /* [10.. 1] */
+		uint32_t func_num		:  3; /* [13..11] */
+		uint32_t b64_en			:  1; /* [14..14] */
+		uint32_t			:  1; /* [15..15] */
+		uint32_t inst_id		:  9; /* [24..16] */
+		uint32_t			:  7; /* [31..25] */
 	};
 	uint32_t raw;
 };
diff --git a/src/soc/amd/turin_poc/include/soc/gpio.h b/src/soc/amd/turin_poc/include/soc/gpio.h
index 613fea7f25..d2890aa50b 100644
--- a/src/soc/amd/turin_poc/include/soc/gpio.h
+++ b/src/soc/amd/turin_poc/include/soc/gpio.h
@@ -25,7 +25,6 @@
 #define GPIO_4				4
 #define GPIO_5				5
 #define GPIO_6				6
-#define GPIO_7				7
 #define GPIO_12				12
 #define GPIO_13				13
 #define GPIO_14				14
@@ -38,15 +37,29 @@
 #define GPIO_23				23
 #define GPIO_24				24
 #define GPIO_26				26
+#define GPIO_27				27
+#define GPIO_28				28
+#define GPIO_29				29
+#define GPIO_30				30
+#define GPIO_31				31
+#define GPIO_32				32
+#define GPIO_40				40
+#define GPIO_42				42
+#define GPIO_70				70
 
 /* Bank 1: GPIO_64 - GPIO_127 */
 #define GPIO_74				74
 #define GPIO_75				75
 #define GPIO_76				76
+#define GPIO_84				84
+#define GPIO_85				85
 #define GPIO_86				86
 #define GPIO_87				87
 #define GPIO_88				88
 #define GPIO_89				89
+#define GPIO_90				90
+#define GPIO_91				91
+#define GPIO_92				92
 #define GPIO_104			104
 #define GPIO_105			105
 #define GPIO_106			106
@@ -54,6 +67,8 @@
 #define GPIO_108			108
 #define GPIO_109			109
 #define GPIO_110			110
+#define GPIO_113			113
+#define GPIO_114			114
 #define GPIO_115			115
 #define GPIO_116			116
 #define GPIO_117			117
@@ -69,6 +84,7 @@
 
 /* Bank 2: GPIO_128 - GPIO_191 */
 #define GPIO_129			129
+#define GPIO_130			130
 #define GPIO_131			131
 #define GPIO_132			132
 #define GPIO_133			133
@@ -78,8 +94,11 @@
 #define GPIO_137			137
 #define GPIO_138			138
 #define GPIO_139			139
+#define GPIO_140			140
 #define GPIO_141			141
 #define GPIO_142			142
+#define GPIO_143			143
+#define GPIO_144			144
 #define GPIO_145			145
 #define GPIO_146			146
 #define GPIO_147			147
@@ -96,16 +115,13 @@
 #define GPIO_259			259
 #define GPIO_260			260
 #define GPIO_261			261
-#define GPIO_262			262
-#define GPIO_263			263
 #define GPIO_264			264
 #define GPIO_265			265
 #define GPIO_266			266
 
 /* IOMUX function names and values */
 #define GPIO_0_IOMUX_PWR_BTN_L 0
-#define GPIO_0_IOMUX_GPIO_PU1PD0 1
-#define GPIO_0_IOMUX_GPIOxx 2
+#define GPIO_0_IOMUX_GPIOxx 1
 #define GPIO_1_IOMUX_SYS_RESET_L 0
 #define GPIO_1_IOMUX_GPIOxx 1
 #define GPIO_2_IOMUX_WAKE_L 0
@@ -121,12 +137,10 @@
 #define GPIO_12_IOMUX_PWRGD_OUT 0
 #define GPIO_12_IOMUX_GPIOxx 1
 #define GPIO_13_IOMUX_I2C4_SCL 0
-#define GPIO_13_IOMUX_CLK_48_24_0 1
-#define GPIO_13_IOMUX_GPIOxx 2
+#define GPIO_13_IOMUX_GPIOxx 1
 #define GPIO_14_IOMUX_I2C4_SDA 0
-#define GPIO_14_IOMUX_S0A3 1
-#define GPIO_14_IOMUX_GPIOxx 2
-#define GPIO_16_IOMUX_USB_1O_OC_L 0
+#define GPIO_14_IOMUX_GPIOxx 1
+#define GPIO_16_IOMUX_USB10_OC_L 0
 #define GPIO_16_IOMUX_GPIOxx 1
 #define GPIO_17_IOMUX_USB11_OC_L 0
 #define GPIO_17_IOMUX_GPIOxx 1
@@ -136,35 +150,52 @@
 #define GPIO_20_IOMUX_I2C5_SDA 0
 #define GPIO_20_IOMUX_SMBUS1_SDA 1
 #define GPIO_20_IOMUX_GPIOxx 2
-#define GPIO_21_IOMUX_GPIOxx 0
-#define GPIO_22_IOMUX_GPIOxx 0
+#define GPIO_21_IOMUX_GPIOxx 2
+#define GPIO_22_IOMUX_GPIOxx 2
 #define GPIO_23_IOMUX_ESPI_RST_OUT_L 0
 #define GPIO_23_IOMUX_GPIOxx 1
 #define GPIO_24_IOMUX_SMERR_L 0
 #define GPIO_24_IOMUX_GPIOxx 1
 #define GPIO_26_IOMUX_PCIE_RST1_L 0
 #define GPIO_26_IOMUX_GPIOxx 1
+#define GPIO_27_IOMUX_GPIOxx 1
+#define GPIO_28_IOMUX_X48M_OUT 0
+#define GPIO_29_IOMUX_GPIOxx 0
+#define GPIO_30_IOMUX_GPIOxx 0
+#define GPIO_31_IOMUX_GPIOxx 0
+#define GPIO_32_IOMUX_GPIOxx 0
+#define GPIO_40_IOMUX_GPIOxx 0
+#define GPIO_42_IOMUX_GPIOxx 0
+#define GPIO_70_IOMUX_GPIOxx 0
 #define GPIO_74_IOMUX_ESPI_CLK2 0
-#define GPIO_74_IOMUX_GPIOxx 1
+#define GPIO_74_IOMUX_GPIOxx 2
 #define GPIO_75_IOMUX_ESPI_CLK1 0
-#define GPIO_75_IOMUX_GPIOxx 1
+#define GPIO_75_IOMUX_GPIOxx 2
 #define GPIO_76_IOMUX_GPIOxx 0
 #define GPIO_76_IOMUX_SPI_TPM_CS_L 1
-#define GPIO_86_IOMUX_NMI_SYNC_FLOOD_L 0
-#define GPIO_87_IOMUX_GPIOxx 0
-#define GPIO_88_IOMUX_GPIOxx 0
+#define GPIO_84_IOMUX_GPIOxx 1
+#define GPIO_85_IOMUX_GPIOxx 1
+#define GPIO_86_IOMUX_GPIOxx 1
+#define GPIO_86_IOMUX_LPC_SMI_L 2
+#define GPIO_87_IOMUX_GPIOxx 2
+#define GPIO_88_IOMUX_GPIOxx 2
 #define GPIO_89_IOMUX_GENINT_L 0
 #define GPIO_89_IOMUX_PM_INTR_L 1
 #define GPIO_89_IOMUX_GPIOxx 2
-#define GPIO_104_IOMUX_GPIOxx 0
-#define GPIO_105_IOMUX_GPIOxx 0
-#define GPIO_106_IOMUX_GPIOxx 0
-#define GPIO_107_IOMUX_GPIOxx 0
+#define GPIO_90_IOMUX_GPIOxx 2
+#define GPIO_91_IOMUX_GPIOxx 1
+#define GPIO_92_IOMUX_GPIOxx 3
+#define GPIO_104_IOMUX_GPIOxx 3
+#define GPIO_105_IOMUX_GPIOxx 3
+#define GPIO_106_IOMUX_GPIOxx 3
+#define GPIO_107_IOMUX_GPIOxx 3
 #define GPIO_108_IOMUX_ESPI0_ALERT_D1 0
-#define GPIO_108_IOMUX_GPIOxx 1
-#define GPIO_109_IOMUX_GPIOxx 0
+#define GPIO_108_IOMUX_GPIOxx 2
+#define GPIO_109_IOMUX_GPIOxx 2
 #define GPIO_110_IOMUX_ESPI1_ALERT_D1 0
 #define GPIO_110_IOMUX_GPIOxx 1
+#define GPIO_113_IOMUX_GPIOxx 2
+#define GPIO_114_IOMUX_GPIOxx 2
 #define GPIO_115_IOMUX_GPIOxx 0
 #define GPIO_115_IOMUX_CLK_REQ11_L 1
 #define GPIO_116_IOMUX_GPIOxx 0
@@ -174,7 +205,7 @@
 #define GPIO_118_IOMUX_SPI_CS0_L 0
 #define GPIO_118_IOMUX_GPIOxx 1
 #define GPIO_119_IOMUX_SPI_CS1_L 0
-#define GPIO_119_IOMUX_GPIOxx 1
+#define GPIO_119_IOMUX_GPIOxx 2
 #define GPIO_120_IOMUX_ESPI0_DATA0 0
 #define GPIO_120_IOMUX_GPIOxx 1
 #define GPIO_121_IOMUX_ESPI0_DATA1 0
@@ -192,8 +223,9 @@
 #define GPIO_129_IOMUX_ESPI_RSTIN_L 0
 #define GPIO_129_IOMUX_KBRST_L 1
 #define GPIO_129_IOMUX_GPIOxx 2
+#define GPIO_130_IOMUX_GPIOxx 1
 #define GPIO_131_IOMUX_ESPI1_DATA0 0
-#define GPIO_131_IOMUX_GPIOxx 1
+#define GPIO_131_IOMUX_GPIOxx 3
 #define GPIO_132_IOMUX_ESPI1_DATA1 0
 #define GPIO_132_IOMUX_GPIOxx 1
 #define GPIO_133_IOMUX_ESPI1_DATA2 0
@@ -212,10 +244,15 @@
 #define GPIO_138_IOMUX_GPIOxx 1
 #define GPIO_139_IOMUX_UART0_INTR 0
 #define GPIO_139_IOMUX_GPIOxx 1
+#define GPIO_140_IOMUX_UART3_RXD 0
+#define GPIO_140_IOMUX_GPIOxx 2
 #define GPIO_141_IOMUX_UART1_RXD 0
 #define GPIO_141_IOMUX_GPIOxx 1
 #define GPIO_142_IOMUX_UART1_TXD 0
-#define GPIO_142_IOMUX_GPIOxx 1
+#define GPIO_142_IOMUX_UART3_TXD 1
+#define GPIO_142_IOMUX_GPIOxx 2
+#define GPIO_143_IOMUX_GPIOxx 1
+#define GPIO_144_IOMUX_GPIOxx 1
 #define GPIO_145_IOMUX_I3C0_SCL_SPD0_SCL 0
 #define GPIO_145_IOMUX_I2C0_SCL_SPD0_SCL 1
 #define GPIO_145_IOMUX_SMBUS0_SCL 2
@@ -258,8 +295,6 @@
 #define GPIO_260_IOMUX_GPIOxx 1
 #define GPIO_261_IOMUX_SGPIO_LOAD 0
 #define GPIO_261_IOMUX_GPIOxx 1
-#define GPIO_262_IOMUX_GPIOxx 0
-#define GPIO_263_IOMUX_GPIOxx 0
 #define GPIO_264_IOMUX_USB00_OC_L 0
 #define GPIO_264_IOMUX_GPIOxx 1
 #define GPIO_265_IOMUX_USB01_OC_L 0
diff --git a/src/soc/amd/turin_poc/include/soc/iomap.h b/src/soc/amd/turin_poc/include/soc/iomap.h
index f1d692121f..d85597e051 100644
--- a/src/soc/amd/turin_poc/include/soc/iomap.h
+++ b/src/soc/amd/turin_poc/include/soc/iomap.h
@@ -8,17 +8,20 @@
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
 #define I3C_CTRLR_COUNT			4
 
+#define ACPIMMIO_RGPIO_BASE		0xfed81200
+
 #define SPI_BASE_ADDRESS		0xfec10000
 
-/* @Todo : Check these values for Turin */
-
-/* I/O Ranges */
-#define ACPI_IO_BASE			0x0400
-#define  ACPI_CSTATE_CONTROL		(ACPI_IO_BASE + 0x10)
+#define FCH_WATCHDOG_BASE		0xfeb00000
 
 /* FCH AL2AHB Registers */
 #define ALINK_AHB_ADDRESS		0xfedc0000
 
+#define APU_DMA0_BASE			0xfedc7000
+#define APU_DMA1_BASE			0xfedc8000
+#define APU_DMA2_BASE			0xfedcc000
+#define APU_DMA3_BASE			0xfedcd000
+
 #define APU_I2C0_BASE			0xfedc2000
 #define APU_I2C1_BASE			0xfedc3000
 #define APU_I2C2_BASE			0xfedc4000
@@ -29,10 +32,25 @@
 #define APU_UART0_BASE			0xfedc9000
 #define APU_UART1_BASE			0xfedca000
 #define APU_UART2_BASE			0xfedce000
+#define APU_UART3_BASE			0xfedcf000
+#define APU_UART4_BASE			0xfedd1000
 
 #define APU_I3C0_BASE			0xfedd2000
 #define APU_I3C1_BASE			0xfedd3000
 #define APU_I3C2_BASE			0xfedd4000
 #define APU_I3C3_BASE			0xfedd6000
 
+/* I/O Ranges */
+#define ACPI_IO_BASE			0x0400
+#define  ACPI_PM_EVT_BLK		(ACPI_IO_BASE + 0x00)
+#define   ACPI_PM1_STS			(ACPI_PM_EVT_BLK + 0x00)
+#define   ACPI_PM1_EN			(ACPI_PM_EVT_BLK + 0x02)
+#define  ACPI_PM1_CNT_BLK		(ACPI_IO_BASE + 0x04)
+#define  ACPI_PM_TMR_BLK		(ACPI_IO_BASE + 0x08)
+#define  ACPI_CSTATE_CONTROL		(ACPI_IO_BASE + 0x10)
+#define  ACPI_GPE0_BLK			(ACPI_IO_BASE + 0x20)
+#define   ACPI_GPE0_STS			(ACPI_GPE0_BLK + 0x00)
+#define   ACPI_GPE0_EN			(ACPI_GPE0_BLK + 0x04)
+#define SMB_BASE_ADDR			0x0b00
+
 #endif /* AMD_TURIN_POC_IOMAP_H */
diff --git a/src/soc/amd/turin_poc/include/soc/msr.h b/src/soc/amd/turin_poc/include/soc/msr.h
index ba2c25f997..a1773b2269 100644
--- a/src/soc/amd/turin_poc/include/soc/msr.h
+++ b/src/soc/amd/turin_poc/include/soc/msr.h
@@ -8,8 +8,8 @@
 /* MSRC001_00[6B:64] P-state [7:0] bit definitions */
 union pstate_msr {
 	struct {
-		uint64_t cpu_fid_0_7	:  8; /* [ 0.. 7] */
-		uint64_t cpu_dfs_id	:  6; /* [ 8..13] */
+		uint64_t cpu_fid_0_11	: 12; /* [ 0..11] */
+		uint64_t		:  2; /* [12..13] */
 		uint64_t cpu_vid_0_7	:  8; /* [14..21] */
 		uint64_t idd_value	:  8; /* [22..29] */
 		uint64_t idd_div	:  2; /* [30..31] */
diff --git a/src/soc/amd/turin_poc/include/soc/smi.h b/src/soc/amd/turin_poc/include/soc/smi.h
index df56b6750f..7712860531 100644
--- a/src/soc/amd/turin_poc/include/soc/smi.h
+++ b/src/soc/amd/turin_poc/include/soc/smi.h
@@ -78,7 +78,8 @@
 /* 31 Reserved */
 #define SMITYPE_WAKE_L2			32
 #define SMITYPE_PSP			33
-/* 34-35 Reserved */
+#define SMITYPE_PSP2			34
+#define SMITYPE_PSP3			35
 #define SMITYPE_ESPI_SCI_B		36
 #define SMITYPE_ESPI1_SYS_EVT_B		37
 #define SMITYPE_ESPI1_WAKE_PME		38
diff --git a/src/soc/amd/turin_poc/include/soc/smu.h b/src/soc/amd/turin_poc/include/soc/smu.h
index dd34044264..e18fc8e3b0 100644
--- a/src/soc/amd/turin_poc/include/soc/smu.h
+++ b/src/soc/amd/turin_poc/include/soc/smu.h
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_POC_SMU_H
-#define AMD_GENOA_POC_SMU_H
+#ifndef AMD_TURIN_POC_SMU_H
+#define AMD_TURIN_POC_SMU_H
 
 /* SMU mailbox register offsets in SMN */
-#define SMN_SMU_MESG_ID		0x3b10530
-#define SMN_SMU_MESG_RESP	0x3b1057c
+#define SMN_SMU_MESG_ID		0x3b10930
+#define SMN_SMU_MESG_RESP	0x3b1097c
 #define SMN_SMU_MESG_ARGS_BASE	0x3b109c4
 
 #define SMU_NUM_ARGS		6
@@ -20,4 +20,4 @@ enum smu_message_id {
  */
 void smu_sx_entry(void);
 
-#endif /* AMD_GENOA_POC_SMU_H */
+#endif /* AMD_TURIN_POC_SMU_H */
diff --git a/src/soc/amd/turin_poc/include/soc/southbridge.h b/src/soc/amd/turin_poc/include/soc/southbridge.h
index 1027a58455..8447b32be7 100644
--- a/src/soc/amd/turin_poc/include/soc/southbridge.h
+++ b/src/soc/amd/turin_poc/include/soc/southbridge.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_POC_SOUTHBRIDGE_H
-#define AMD_GENOA_POC_SOUTHBRIDGE_H
+#ifndef AMD_TURIN_POC_SOUTHBRIDGE_H
+#define AMD_TURIN_POC_SOUTHBRIDGE_H
 
 #include <soc/iomap.h>
 
@@ -9,6 +9,7 @@
 #define PM_ISACONTROL			0x04
 #define   ABCLKGATEEN			BIT(16)
 #define PM_PCI_CTRL			0x08
+#define   FORCE_STPCLK_RETRY		BIT(24)
 #define   FORCE_SLPSTATE_RETRY		BIT(25)
 #define PWR_RESET_CFG			0x10
 #define   TOGGLE_ALL_PWR_GOOD		(1 << 1)
@@ -72,8 +73,6 @@
 #define   PM_ACPI_RTC_WAKE_EN		BIT(29)
 #define   PM_ACPI_USE_GATED_ALINK_CLK	BIT(30)
 #define   PM_ACPI_DELAY_GPP_OFF_TIME	BIT(31)
-#define PM_SPI_PAD_PU_PD		0x90
-#define   PM_ESPI_CS_USE_DATA2		BIT(16)
 #define PM_LPC_GATING			0xec
 #define   PM_LPC_AB_NO_BYPASS_EN	BIT(2)
 #define   PM_LPC_A20_EN			BIT(1)
@@ -119,4 +118,4 @@ void fch_pre_init(void);
 void fch_early_init(void);
 void fch_init(void *chip_info);
 
-#endif /* AMD_GENOA_POC_SOUTHBRIDGE_H */
+#endif /* AMD_TURIN_POC_SOUTHBRIDGE_H */
diff --git a/src/soc/amd/turin_poc/include/soc/xhci.h b/src/soc/amd/turin_poc/include/soc/xhci.h
new file mode 100644
index 0000000000..4645a629d2
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/xhci.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_XHCI_H
+#define AMD_TURIN_XHCI_H
+
+#include <static.h>
+
+#define SOC_XHCI_0 DEV_PTR(xhci_0)
+#define SOC_XHCI_1 DEV_PTR(xhci_1)
+#define SOC_XHCI_2 NULL
+#define SOC_XHCI_3 NULL
+#define SOC_XHCI_4 NULL
+#define SOC_XHCI_5 NULL
+#define SOC_XHCI_6 NULL
+#define SOC_XHCI_7 NULL
+
+#endif /* AMD_TURIN_XHCI_H */
diff --git a/src/soc/amd/turin_poc/mca.c b/src/soc/amd/turin_poc/mca.c
index 9a6df2b53e..460d9afee2 100644
--- a/src/soc/amd/turin_poc/mca.c
+++ b/src/soc/amd/turin_poc/mca.c
@@ -4,7 +4,11 @@
 #include <cpu/x86/msr.h>
 #include <types.h>
 
-/* TODO: Check if non-core MCA banks are same for all cores */
+/*
+ * Non-core MCA banks are not the same for all cores.
+ * Refer to "Table 56: Non-core MCA Bank to Block Mapping"
+ * in Turin C1 PPR (doc 57238).
+ */
 static const char *const mca_bank_name[] = {
 	[0]  = "Load-store unit",
 	[1]  = "Instruction fetch unit",
@@ -22,22 +26,22 @@ static const char *const mca_bank_name[] = {
 	[13] = "L3 cache unit",
 	[14] = "L3 cache unit",
 	[15] = "Microprocessor5 Management Controller",
-	[16] = "Parameter Block",
-	[17] = "GMI Controller",
-	[18] = "GMI Controller",
-	[19] = "High Speed Interface Unit (GMI)",
-	[20] = "High Speed Interface Unit (GMI)",
+	[16] = "GMI Controller (PCS_GMI)",
+	[17] = "GMI Controller (PCS_GMI)",
+	[18] = "High Speed Interface Unit (KPX_GMI)",
+	[19] = "High Speed Interface Unit (KPX_GMI)",
+	[20] = "MPDMA",
 	[21] = "Unified Memory Controller",
 	[22] = "Unified Memory Controller",
 	[23] = "Coherent Station",
 	[24] = "Coherent Station",
-	[25] = "Northbridge IO Unit",
-	[26] = "PCIe Root Port",
-	[27] = "PCIe Root Port",
-	[28] = "Power Management, Interrupts, Etc.",
+	[25] = "PCIE",
+	[26] = "SATA",
+	[27] = "Northbridge IO Unit",
+	[28] = "NBIF",
 	[29] = "SMU",
-	[30] = "XGMI Controller",
-	[31] = "High Speed Interface Unit (XGMI)",
+	[30] = "Power Management, Interrupts, Etc.",
+	[31] = "High Speed Interface Unit (SERDES)",
 };
 
 bool mca_has_expected_bank_count(void)
diff --git a/src/soc/amd/turin_poc/root_complex.c b/src/soc/amd/turin_poc/root_complex.c
index 3171febe9f..ffff6d1c32 100644
--- a/src/soc/amd/turin_poc/root_complex.c
+++ b/src/soc/amd/turin_poc/root_complex.c
@@ -2,24 +2,52 @@
 
 #include <amdblocks/ioapic.h>
 #include <amdblocks/root_complex.h>
+#include <device/device.h>
+#include <device/pci.h>
 #include <types.h>
 
+/*
+ * The order of IOHCs here is not random. They are sorted so that:
+ * 1. The First IOHC is the one with primary FCH. We want the LPC/SMBUS
+ *    devices be on bus 0.
+ * 2. The rest of IOHCs are listed in an order so that ECAM MMIO region is one
+ *    continuous block for all domains.
+ *
+ * AGESA/OpenSIL sets up the PCI configuration decoding ranges in line with
+ * this.
+ */
 static const struct domain_iohc_info iohc_info[] = {
 	[0] = {
-		.fabric_id = 0x22,
-		.misc_smn_base = SMN_IOHC_MISC_BASE_13C1,
+		.fabric_id = 0x24,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_13D1,
 	},
 	[1] = {
-		.fabric_id = 0x23,
-		.misc_smn_base = SMN_IOHC_MISC_BASE_13B1,
+		.fabric_id = 0x25,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_1D61,
 	},
 	[2] = {
-		.fabric_id = 0x21,
+		.fabric_id = 0x26,
 		.misc_smn_base = SMN_IOHC_MISC_BASE_13E1,
 	},
 	[3] = {
+		.fabric_id = 0x27,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_1D51,
+	},
+	[4] = {
+		.fabric_id = 0x23,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_1D41,
+	},
+	[5] = {
+		.fabric_id = 0x22,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_13C1,
+	},
+	[6] = {
+		.fabric_id = 0x21,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_1D71,
+	},
+	[7] = {
 		.fabric_id = 0x20,
-		.misc_smn_base = SMN_IOHC_MISC_BASE_13D1,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_13B1,
 	},
 };
 
@@ -33,15 +61,18 @@ static const struct non_pci_mmio_reg non_pci_mmio[] = {
 	{ 0x2d8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x2e0, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x2e8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
-	/* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we
-	   tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB
-	   resource. */
-	{ 0x2f0, 0xffffffffff00ull,   4 * KiB, IOMMU_IOAPIC_IDX },
+	/*
+	 * The hardware has a 256 byte alignment requirement for the IOAPIC
+	 * MMIO base, but OpenSIL configures 64k-aligned base address and this
+	 * is reported as 256 byte resource.
+	 */
+	{ 0x2f0, 0xffffffffff00ull,	  256, IOMMU_IOAPIC_IDX },
 	{ 0x2f8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x300, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x308, 0xfffffffff000ull,   4 * KiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x310, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO },
+	{ 0x338, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 };
 
 const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count)
@@ -49,3 +80,17 @@ const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count)
 	*count = ARRAY_SIZE(non_pci_mmio);
 	return non_pci_mmio;
 }
+
+static const char *gnb_acpi_name(const struct device *dev)
+{
+	return "GNB";
+}
+
+struct device_operations turin_root_complex_operations = {
+	/* The root complex has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.acpi_name		= gnb_acpi_name,
+};
diff --git a/src/soc/amd/turin_poc/smihandler.c b/src/soc/amd/turin_poc/smihandler.c
index 1eb051317b..80185a843d 100644
--- a/src/soc/amd/turin_poc/smihandler.c
+++ b/src/soc/amd/turin_poc/smihandler.c
@@ -61,6 +61,7 @@ static void fch_slp_typ_handler(void)
 		/* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */
 		pci_ctrl = pm_read32(PM_PCI_CTRL);
 		pci_ctrl &= ~FORCE_SLPSTATE_RETRY;
+		pci_ctrl |= FORCE_STPCLK_RETRY;
 		pm_write32(PM_PCI_CTRL, pci_ctrl);
 
 		/* Enable SlpTyp */
diff --git a/src/soc/amd/turin_poc/uart.c b/src/soc/amd/turin_poc/uart.c
index 19f7746bc8..c90485318f 100644
--- a/src/soc/amd/turin_poc/uart.c
+++ b/src/soc/amd/turin_poc/uart.c
@@ -24,6 +24,10 @@ static const struct soc_uart_ctrlr_info uart_info[] = {
 			PAD_NF(GPIO_137, UART2_RXD, PULL_NONE),
 			PAD_NF(GPIO_135, UART2_TXD, PULL_NONE),
 		} },
+	[3] =	{ APU_UART2_BASE, FCH_AOAC_DEV_UART3, "FUR3", {
+			PAD_NF(GPIO_140, UART3_RXD, PULL_NONE),
+			PAD_NF(GPIO_142, UART3_TXD, PULL_NONE),
+		} },
 };
 
 const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs)