This patch:
* Moves non-DRAM early init code out of initram and into stage1, where it should have been in the first place * Fixes an issue with GP3 timer causing system reboot (possibly not present in current svn, but was present in my local copy) * Fixes serial garbage from stage1 on jetway j7f2 * Fixes ROM mapping for flash > 512k on vt8237 * Makes a couple minor whitespace changes * Moves some function prototypes to the headers where they belong * Nukes some phase2 hackery that belongs in phase4 (eventually) * Comments out early_mtrr_init() for via/epia-cn, this breaks booting on jetway j7f2 * Moves troublesome SATA init code into stage1 - change of device class hangs coreboot * Gets to vt8237 IDE phase6 init and dies on jetway/j7f2: Phase 6: Initializing devices... Phase 6: Root Device init. Phase 6: PCI: 00:10.1 init. Primary IDE interface enabled Secondary IDE interface enabled <hang> Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1070 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Corey Osgood
parent
539a101e1b
commit
68529567e4
16 changed files with 295 additions and 348 deletions
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@ -35,6 +35,7 @@
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void x86_setup_var_mtrrs(unsigned address_bits);
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void x86_setup_mtrrs(unsigned address_bits);
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int x86_mtrr_check(void);
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void early_mtrr_init(void);
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#endif
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@ -21,11 +21,12 @@
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## TODO
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STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
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$(src)/northbridge/via/cn700/stage1.c \
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$(src)/southbridge/via/vt8237/stage1.c \
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$(src)/arch/x86/stage1_mtrr.c
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INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
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$(src)/northbridge/via/cn700/initram.c \
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$(src)/southbridge/via/vt8237/stage1.c \
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$(src)/lib/ramtest.c \
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$(src)/arch/x86/pci_ops_conf1.c
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@ -22,13 +22,9 @@
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <io.h>
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#include <spd.h>
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#include <via_c7.h>
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#include <arch/x86/pci_ops.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <superio/fintek/f71805f/f71805f.h>
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#include <southbridge/via/vt8237/vt8237.h>
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#include <northbridge/via/cn700/cn700.h>
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@ -65,7 +61,7 @@ void find_smbus_devices(u8 min, u8 max)
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void dump_smbus_registers(void)
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{
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int device;
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for(device = 1; device < (int)0x80; device++) {
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for(device = (int)0x50; device < (int)0x52; device++) {
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int j;
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//if(spd_read_byte(device, 0) < 0 )
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// continue;
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@ -87,100 +83,9 @@ void dump_smbus_registers(void)
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}
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}
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static void enable_mainboard_devices(void)
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{
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u32 dev;
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pci_conf1_find_device(0x1106, 0x3227, &dev);
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/* Disable GP3 */
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pci_conf1_write_config8(dev, 0x98, 0x00);
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pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata
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pci_conf1_write_config8(dev, 0x51, 0x1f);
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pci_conf1_write_config8(dev, 0x58, 0x60);
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pci_conf1_write_config8(dev, 0x59, 0x80);
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pci_conf1_write_config8(dev, 0x5b, 0x08);
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pci_conf1_find_device(0x1106, 0x0571, &dev);
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/* Make it respond to IO space */
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pci_conf1_write_config8(dev, 0x04, 0x07);
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/* Compatibility mode addresses */
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//pci_conf1_write_config32(dev, 0x10, 0);
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//pci_conf1_write_config32(dev, 0x14, 0);
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//pci_conf1_write_config32(dev, 0x18, 0);
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//pci_conf1_write_config32(dev, 0x1b, 0);
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/* Native mode base address */
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//pci_conf1_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
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pci_conf1_write_config8(dev, 0x40, 0x4b);//was 0x3
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pci_conf1_write_config8(dev, 0x41, 0xf2);
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pci_conf1_write_config8(dev, 0x42, 0x09);
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/* I'll be damned if I know what these do */
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pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e
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pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00
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}
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static void enable_shadow_ram(void)
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{
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u8 shadowreg;
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printk(BIOS_DEBUG, "Enabling shadow ram\n");
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/* Enable shadow ram as normal dram */
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/* 0xc0000-0xcffff */
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff);
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/* 0xd0000-0xdffff */
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff);
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/* 0xe0000-0xeffff */
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff);
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/* 0xf0000-0xfffff */
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shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83);
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shadowreg |= 0x30;
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg);
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/* Do it again for the vlink controller */
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shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63);
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shadowreg |= 0x30;
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg);
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}
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static void enable_vlink(void)
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{
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printk(BIOS_DEBUG, "Enabling Via V-Link\n");
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/* Enable V-Link statically in 8x mode, using Jetway default values */
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//40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04);
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//pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01);
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//b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77);
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/* This has to be done last, I think */
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
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}
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int main(void)
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{
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/* TODO: Kill off this struct, like Uwe's doing in v2 */
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struct board_info ctrl[] = {
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{
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.d0f2 = PCI_BDF(0, 0, 2),
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@ -194,14 +99,7 @@ int main(void)
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printk(BIOS_DEBUG, "In initram.c main()\n");
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enable_vlink();
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enable_mainboard_devices();
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enable_shadow_ram();
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c7_cpu_setup(PCI_BDF(0, 0, 2));
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enable_smbus(SMBUS_IO_BASE);
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//find_smbus_devices(0x00, 0xff);
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//dump_smbus_registers();
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sdram_set_registers(ctrl);
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sdram_set_spd_registers(ctrl);
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ddr2_sdram_enable(ctrl);
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@ -19,33 +19,27 @@
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <io.h>
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#include <arch/x86/pci_ops.h>
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#include <arch/x86/mtrr.h>
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#include <arch/x86/legacy.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <superio/fintek/f71805f/f71805f.h>
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#include <northbridge/via/cn700/cn700.h>
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#include <southbridge/via/vt8237/vt8237.h>
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#define SMBUS_IO_BASE 0x0400
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void hardware_stage1(void)
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{
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u32 dev;
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post_code(POST_START_OF_MAIN);
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f71805f_enable_serial(0x2e);
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/* Enable multifunction for northbridge. */
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pci_conf1_write_config8(0x00, 0x4f, 0x01);
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uart_init();
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printk(BIOS_SPEW, "In hardware_stage1()\n");
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/* Disabled GP3, to keep the system from rebooting automatically */
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//pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev);
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dev = PCI_BDF(0, 17, 0);
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pci_conf1_write_config8(dev, 0x98, 0x00);
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cn700_stage1();
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vt8237_stage1(SMBUS_IO_BASE);
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}
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void mainboard_pre_payload(void)
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{
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//banner(BIOS_DEBUG, "mainboard_pre_payload: done");
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}
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@ -20,11 +20,12 @@
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STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
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$(src)/arch/x86/stage1_mtrr.c \
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$(src)/mainboard/$(MAINBOARDDIR)/stage1.c
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$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
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$(src)/southbridge/via/vt8237/stage1.c \
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$(src)/northbridge/via/cn700/stage1.c \
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INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
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$(src)/northbridge/via/cn700/initram.c \
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$(src)/southbridge/via/vt8237/stage1.c \
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$(src)/lib/ramtest.c
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STAGE2_MAINBOARD_SRC =
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@ -22,12 +22,9 @@
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <io.h>
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#include <spd.h>
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#include <via_c7.h>
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#include <arch/x86/pci_ops.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <superio/via/vt1211/vt1211.h>
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#include <southbridge/via/vt8237/vt8237.h>
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#include <northbridge/via/cn700/cn700.h>
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@ -87,98 +84,6 @@ void dump_smbus_registers(void)
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}
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}
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static void enable_mainboard_devices(void)
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{
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u32 dev;
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pci_conf1_find_device(0x1106, 0x3227, &dev);
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/* Disable GP3 */
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pci_conf1_write_config8(dev, 0x98, 0x00);
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pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata
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pci_conf1_write_config8(dev, 0x51, 0x1f);
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pci_conf1_write_config8(dev, 0x58, 0x60);
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pci_conf1_write_config8(dev, 0x59, 0x80);
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pci_conf1_write_config8(dev, 0x5b, 0x08);
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pci_conf1_find_device(0x1106, 0x0571, &dev);
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/* Make it respond to IO space */
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pci_conf1_write_config8(dev, 0x04, 0x07);
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/* Compatibility mode addresses */
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//pci_conf1_write_config32(dev, 0x10, 0);
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//pci_conf1_write_config32(dev, 0x14, 0);
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//pci_conf1_write_config32(dev, 0x18, 0);
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//pci_conf1_write_config32(dev, 0x1b, 0);
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/* Native mode base address */
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//pci_conf1_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
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pci_conf1_write_config8(dev, 0x40, 0x4b);//was 0x3
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pci_conf1_write_config8(dev, 0x41, 0xf2);
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pci_conf1_write_config8(dev, 0x42, 0x09);
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/* I'll be damned if I know what these do */
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pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e
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pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00
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}
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static void enable_shadow_ram(void)
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{
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u8 shadowreg;
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printk(BIOS_DEBUG, "Enabling shadow ram\n");
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/* Enable shadow ram as normal dram */
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/* 0xc0000-0xcffff */
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff);
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/* 0xd0000-0xdffff */
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff);
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/* 0xe0000-0xeffff */
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff);
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/* 0xf0000-0xfffff */
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shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83);
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shadowreg |= 0x30;
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg);
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/* Do it again for the vlink controller */
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shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63);
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shadowreg |= 0x30;
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg);
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}
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static void enable_vlink(void)
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{
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printk(BIOS_DEBUG, "Enabling Via V-Link\n");
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/* Enable V-Link statically in 8x mode, using Jetway default values */
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//40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04);
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//pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01);
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//b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77);
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/* This has to be done last, I think */
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
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}
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int main(void)
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{
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struct board_info ctrl[] = {
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@ -194,14 +99,6 @@ int main(void)
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printk(BIOS_DEBUG, "In initram.c main()\n");
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enable_vlink();
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enable_mainboard_devices();
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enable_shadow_ram();
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c7_cpu_setup(PCI_BDF(0, 0, 2));
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enable_smbus(SMBUS_IO_BASE);
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//find_smbus_devices(0x00, 0xff);
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sdram_set_registers(ctrl);
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sdram_set_spd_registers(ctrl);
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ddr2_sdram_enable(ctrl);
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@ -22,37 +22,28 @@
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#include <types.h>
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#include <lib.h>
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#include <console.h>
|
||||
#include <io.h>
|
||||
#include <arch/x86/pci_ops.h>
|
||||
#include <arch/x86/mtrr.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <superio/fintek/f71805f/f71805f.h>
|
||||
#include <northbridge/via/cn700/cn700.h>
|
||||
#include <southbridge/via/vt8237/vt8237.h>
|
||||
#include <superio/via/vt1211/vt1211.h>
|
||||
|
||||
#define SMBUS_IO_BASE 0x400
|
||||
|
||||
void hardware_stage1(void)
|
||||
{
|
||||
void early_mtrr_init(void);
|
||||
void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase);
|
||||
u32 dev;
|
||||
|
||||
post_code(POST_START_OF_MAIN);
|
||||
|
||||
/* do this or watch the system run slowly */
|
||||
early_mtrr_init();
|
||||
/* do this and the system won't run at all */
|
||||
//early_mtrr_init();
|
||||
|
||||
vt1211_enable_serial(0x2e, 2, 0x3f8);
|
||||
|
||||
/* Enable multifunction for northbridge. */
|
||||
pci_conf1_write_config8(0x00, 0x4f, 0x01);
|
||||
|
||||
printk(BIOS_SPEW, "In hardware_stage1()\n");
|
||||
/* Disabled GP3, to keep the system from rebooting automatically */
|
||||
//pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev);
|
||||
dev = PCI_BDF(0, 17, 0);
|
||||
pci_conf1_write_config8(dev, 0x98, 0x00);
|
||||
cn700_stage1();
|
||||
vt8237_stage1(SMBUS_IO_BASE);
|
||||
}
|
||||
|
||||
void mainboard_pre_payload(void)
|
||||
{
|
||||
//banner(BIOS_DEBUG, "mainboard_pre_payload: done");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ struct board_info {
|
|||
u16 spd_channel0[2];
|
||||
};
|
||||
|
||||
void c7_cpu_setup(u32);
|
||||
void cn700_stage1(void);
|
||||
void sdram_set_registers(struct board_info *);
|
||||
void sdram_set_spd_registers(struct board_info *);
|
||||
void ddr2_sdram_enable(struct board_info *);
|
||||
|
|
|
|||
|
|
@ -127,97 +127,6 @@ static void do_ram_command(struct board_info *dev, u8 command, u32 addr_offset)
|
|||
printk(BIOS_SPEW, "\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* Configure the bus between the cpu and the northbridge. This might be able to
|
||||
* be moved to post-ram code in the future. For the most part, these registers
|
||||
* should not be messed around with. These are too complex to explain short of
|
||||
* copying the datasheets into the comments, but most of these values are from
|
||||
* the BIOS Porting Guide, so they should work on any board. If they don't,
|
||||
* try the values from your factory BIOS.
|
||||
*
|
||||
* TODO: Changing the DRAM frequency doesn't work (hard lockup)
|
||||
*
|
||||
* @param dev The northbridge's CPU Host Interface (D0F2)
|
||||
*/
|
||||
void c7_cpu_setup(u32 dev)
|
||||
{
|
||||
/* Host bus interface registers (D0F2 0x50-0x67) */
|
||||
/* Request phase control */
|
||||
pci_conf1_write_config8(dev, 0x50, 0x88);
|
||||
/* CPU Interface Control */
|
||||
pci_conf1_write_config8(dev, 0x51, 0x7a);
|
||||
pci_conf1_write_config8(dev, 0x52, 0x6f);
|
||||
/* Arbitration */
|
||||
pci_conf1_write_config8(dev, 0x53, 0x88);
|
||||
/* Miscellaneous Control */
|
||||
pci_conf1_write_config8(dev, 0x54, 0x1e);
|
||||
pci_conf1_write_config8(dev, 0x55, 0x16);
|
||||
/* Write Policy */
|
||||
pci_conf1_write_config8(dev, 0x56, 0x01);
|
||||
/* Miscellaneous Control */
|
||||
/* DRAM Operating Frequency (bits 7:5 Rx57)
|
||||
* 000 : 100MHz 001 : 133MHz
|
||||
* 010 : 166MHz 011 : 200MHz
|
||||
* 100 : 266MHz 101 : 333MHz
|
||||
* 110/111 : Reserved
|
||||
* bits 4:0: Reserved
|
||||
*/
|
||||
/* CPU Miscellaneous Control */
|
||||
pci_conf1_write_config8(dev, 0x59, 0x44);
|
||||
/* Write Policy */
|
||||
pci_conf1_write_config8(dev, 0x5d, 0xb2);
|
||||
/* Bandwidth Timer */
|
||||
pci_conf1_write_config8(dev, 0x5e, 0x88);
|
||||
/* CPU Miscellaneous Control */
|
||||
pci_conf1_write_config8(dev, 0x5f, 0xc7);
|
||||
|
||||
/* Line DRDY# Timing Control */
|
||||
pci_conf1_write_config8(dev, 0x60, 0xff);
|
||||
pci_conf1_write_config8(dev, 0x61, 0xff);
|
||||
pci_conf1_write_config8(dev, 0x62, 0x0f);
|
||||
/* QW DRDY# Timing Control */
|
||||
pci_conf1_write_config8(dev, 0x63, 0xff);
|
||||
pci_conf1_write_config8(dev, 0x64, 0xff);
|
||||
pci_conf1_write_config8(dev, 0x65, 0x0f);
|
||||
/* Read Line Burst DRDY# Timing Control */
|
||||
pci_conf1_write_config8(dev, 0x66, 0xff);
|
||||
pci_conf1_write_config8(dev, 0x67, 0x30);
|
||||
|
||||
/* Host Bus I/O Circuit (see datasheet) */
|
||||
/* Host Address Pullup/down Driving */
|
||||
pci_conf1_write_config8(dev, 0x70, 0x11);
|
||||
pci_conf1_write_config8(dev, 0x71, 0x11);
|
||||
pci_conf1_write_config8(dev, 0x72, 0x11);
|
||||
pci_conf1_write_config8(dev, 0x73, 0x11);
|
||||
/* Miscellaneous Control */
|
||||
pci_conf1_write_config8(dev, 0x74, 0x35);
|
||||
/* AGTL+ I/O Circuit */
|
||||
pci_conf1_write_config8(dev, 0x75, 0x28);
|
||||
/* AGTL+ Compensation Status */
|
||||
pci_conf1_write_config8(dev, 0x76, 0x74);
|
||||
/* AGTL+ Auto Compensation Offest */
|
||||
pci_conf1_write_config8(dev, 0x77, 0x00);
|
||||
/* Host FSB CKG Control */
|
||||
pci_conf1_write_config8(dev, 0x78, 0x0a);
|
||||
/* Address/Address Clock Output Delay Control */
|
||||
pci_conf1_write_config8(dev, 0x79, 0xaa);
|
||||
/* Address Strobe Input Delay Control */
|
||||
pci_conf1_write_config8(dev, 0x7a, 0x24);
|
||||
/* Address CKG Rising/Falling Time Control */
|
||||
pci_conf1_write_config8(dev, 0x7b, 0xaa);
|
||||
/* Address CKG Clock Rising/Falling Time Control */
|
||||
pci_conf1_write_config8(dev, 0x7c, 0x00);
|
||||
/* Undefined (can't remember why I did this) */
|
||||
pci_conf1_write_config8(dev, 0x7d, 0x6d);
|
||||
|
||||
pci_conf1_write_config8(dev, 0x7e, 0x00);
|
||||
pci_conf1_write_config8(dev, 0x7f, 0x00);
|
||||
pci_conf1_write_config8(dev, 0x80, 0x1b);
|
||||
pci_conf1_write_config8(dev, 0x81, 0x0a);
|
||||
pci_conf1_write_config8(dev, 0x82, 0x0a);
|
||||
pci_conf1_write_config8(dev, 0x83, 0x0a);
|
||||
}
|
||||
|
||||
/**
|
||||
* Set up various ram and other control registers statically. Some of these may
|
||||
* not be needed, other should be done with spd info, but that's a project for
|
||||
|
|
@ -353,10 +262,6 @@ void sdram_set_registers(struct board_info *dev)
|
|||
pci_conf1_write_config8(dev->d0f3, 0x74, 0x04);
|
||||
pci_conf1_write_config8(dev->d0f3, 0x75, 0x04);
|
||||
pci_conf1_write_config8(dev->d0f3, 0x76, 0x00);
|
||||
|
||||
/* Thanks to Urbez Santana Roma for this */
|
||||
pci_conf1_write_config8(dev->d1f0, 0x19, 0x1);
|
||||
pci_conf1_write_config8(dev->d1f0, 0x1a, 0x1);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
185
northbridge/via/cn700/stage1.c
Normal file
185
northbridge/via/cn700/stage1.c
Normal file
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 Corey Osgood <corey.osgood@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <device/pci.h>
|
||||
#include <config.h>
|
||||
#include "cn700.h"
|
||||
|
||||
static void enable_shadow_ram(void)
|
||||
{
|
||||
u8 shadowreg;
|
||||
|
||||
printk(BIOS_DEBUG, "Enabling shadow ram\n");
|
||||
/* Enable shadow ram as normal dram */
|
||||
/* 0xc0000-0xcffff */
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff);
|
||||
/* 0xd0000-0xdffff */
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff);
|
||||
/* 0xe0000-0xeffff */
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff);
|
||||
|
||||
/* 0xf0000-0xfffff */
|
||||
shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83);
|
||||
shadowreg |= 0x30;
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg);
|
||||
|
||||
/* Do it again for the vlink controller */
|
||||
shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63);
|
||||
shadowreg |= 0x30;
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg);
|
||||
}
|
||||
|
||||
static void enable_vlink(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Enabling Via V-Link\n");
|
||||
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04);
|
||||
//pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77);
|
||||
|
||||
/* This has to be done last, I think */
|
||||
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
|
||||
}
|
||||
|
||||
/**
|
||||
* Configure the bus between the cpu and the northbridge. This might be able to
|
||||
* be moved to post-ram code in the future. For the most part, these registers
|
||||
* should not be messed around with. These are too complex to explain short of
|
||||
* copying the datasheets into the comments, but most of these values are from
|
||||
* the BIOS Porting Guide, so they should work on any board. If they don't,
|
||||
* try the values from your factory BIOS.
|
||||
*
|
||||
* TODO: Changing the DRAM frequency doesn't work (hard lockup)
|
||||
*
|
||||
* @param dev The northbridge's CPU Host Interface (D0F2)
|
||||
*/
|
||||
static void c7_cpu_setup(void)
|
||||
{
|
||||
u32 dev = PCI_BDF(0, 0, 2);
|
||||
|
||||
/* Host bus interface registers (D0F2 0x50-0x67) */
|
||||
/* Request phase control */
|
||||
pci_conf1_write_config8(dev, 0x50, 0x88);
|
||||
/* CPU Interface Control */
|
||||
pci_conf1_write_config8(dev, 0x51, 0x7a);
|
||||
pci_conf1_write_config8(dev, 0x52, 0x6f);
|
||||
/* Arbitration */
|
||||
pci_conf1_write_config8(dev, 0x53, 0x88);
|
||||
/* Miscellaneous Control */
|
||||
pci_conf1_write_config8(dev, 0x54, 0x1e);
|
||||
pci_conf1_write_config8(dev, 0x55, 0x16);
|
||||
/* Write Policy */
|
||||
pci_conf1_write_config8(dev, 0x56, 0x01);
|
||||
/* Miscellaneous Control */
|
||||
/* DRAM Operating Frequency (bits 7:5 Rx57)
|
||||
* 000 : 100MHz 001 : 133MHz
|
||||
* 010 : 166MHz 011 : 200MHz
|
||||
* 100 : 266MHz 101 : 333MHz
|
||||
* 110/111 : Reserved
|
||||
* bits 4:0: Reserved
|
||||
*/
|
||||
/* CPU Miscellaneous Control */
|
||||
pci_conf1_write_config8(dev, 0x59, 0x44);
|
||||
/* Write Policy */
|
||||
pci_conf1_write_config8(dev, 0x5d, 0xb2);
|
||||
/* Bandwidth Timer */
|
||||
pci_conf1_write_config8(dev, 0x5e, 0x88);
|
||||
/* CPU Miscellaneous Control */
|
||||
pci_conf1_write_config8(dev, 0x5f, 0xc7);
|
||||
|
||||
/* Line DRDY# Timing Control */
|
||||
pci_conf1_write_config8(dev, 0x60, 0xff);
|
||||
pci_conf1_write_config8(dev, 0x61, 0xff);
|
||||
pci_conf1_write_config8(dev, 0x62, 0x0f);
|
||||
/* QW DRDY# Timing Control */
|
||||
pci_conf1_write_config8(dev, 0x63, 0xff);
|
||||
pci_conf1_write_config8(dev, 0x64, 0xff);
|
||||
pci_conf1_write_config8(dev, 0x65, 0x0f);
|
||||
/* Read Line Burst DRDY# Timing Control */
|
||||
pci_conf1_write_config8(dev, 0x66, 0xff);
|
||||
pci_conf1_write_config8(dev, 0x67, 0x30);
|
||||
|
||||
/* Host Bus I/O Circuit (see datasheet) */
|
||||
/* Host Address Pullup/down Driving */
|
||||
pci_conf1_write_config8(dev, 0x70, 0x11);
|
||||
pci_conf1_write_config8(dev, 0x71, 0x11);
|
||||
pci_conf1_write_config8(dev, 0x72, 0x11);
|
||||
pci_conf1_write_config8(dev, 0x73, 0x11);
|
||||
/* Miscellaneous Control */
|
||||
pci_conf1_write_config8(dev, 0x74, 0x35);
|
||||
/* AGTL+ I/O Circuit */
|
||||
pci_conf1_write_config8(dev, 0x75, 0x28);
|
||||
/* AGTL+ Compensation Status */
|
||||
pci_conf1_write_config8(dev, 0x76, 0x74);
|
||||
/* AGTL+ Auto Compensation Offest */
|
||||
pci_conf1_write_config8(dev, 0x77, 0x00);
|
||||
/* Host FSB CKG Control */
|
||||
pci_conf1_write_config8(dev, 0x78, 0x0a);
|
||||
/* Address/Address Clock Output Delay Control */
|
||||
pci_conf1_write_config8(dev, 0x79, 0xaa);
|
||||
/* Address Strobe Input Delay Control */
|
||||
pci_conf1_write_config8(dev, 0x7a, 0x24);
|
||||
/* Address CKG Rising/Falling Time Control */
|
||||
pci_conf1_write_config8(dev, 0x7b, 0xaa);
|
||||
/* Address CKG Clock Rising/Falling Time Control */
|
||||
pci_conf1_write_config8(dev, 0x7c, 0x00);
|
||||
/* Undefined (can't remember why I did this) */
|
||||
pci_conf1_write_config8(dev, 0x7d, 0x6d);
|
||||
|
||||
pci_conf1_write_config8(dev, 0x7e, 0x00);
|
||||
pci_conf1_write_config8(dev, 0x7f, 0x00);
|
||||
pci_conf1_write_config8(dev, 0x80, 0x1b);
|
||||
pci_conf1_write_config8(dev, 0x81, 0x0a);
|
||||
pci_conf1_write_config8(dev, 0x82, 0x0a);
|
||||
pci_conf1_write_config8(dev, 0x83, 0x0a);
|
||||
}
|
||||
|
||||
void cn700_stage1(void)
|
||||
{
|
||||
/* Enable multifunction for northbridge. */
|
||||
pci_conf1_write_config8(0x00, 0x4f, 0x01);
|
||||
|
||||
/* Put Bus 1 in its proper place */
|
||||
pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x19, 0x1);
|
||||
pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x1a, 0x1);
|
||||
|
||||
enable_shadow_ram();
|
||||
enable_vlink();
|
||||
c7_cpu_setup();
|
||||
}
|
||||
|
|
@ -95,8 +95,8 @@ struct device_operations vt8237_ide = {
|
|||
{.pci = {.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_VT8237_PATA}}},
|
||||
.constructor = default_device_constructor,
|
||||
.phase2_fixup = vt8237_enable,
|
||||
.phase3_scan = 0,
|
||||
//.phase2_fixup = vt8237_enable,
|
||||
//.phase3_scan = 0,
|
||||
//.phase4_enable_disable = vt8237_enable,
|
||||
//.phase4_read_resources = pci_dev_read_resources,
|
||||
//.phase4_set_resources = pci_set_resources,
|
||||
|
|
|
|||
|
|
@ -448,7 +448,6 @@ struct device_operations vt8237r_lpc = {
|
|||
{.pci = {.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_VT8237R_LPC}}},
|
||||
.constructor = default_device_constructor,
|
||||
.phase2_fixup = vt8237_enable,
|
||||
.phase3_scan = scan_static_bus,
|
||||
.phase4_read_resources = vt8237_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
|
|
@ -461,7 +460,6 @@ struct device_operations vt8237s_lpc = {
|
|||
{.pci = {.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_VT8237S_LPC}}},
|
||||
.constructor = default_device_constructor,
|
||||
.phase2_fixup = vt8237_enable,
|
||||
.phase3_scan = scan_static_bus,
|
||||
.phase4_read_resources = vt8237_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
|
|
|
|||
|
|
@ -23,6 +23,9 @@
|
|||
#include "vt8237.h"
|
||||
|
||||
/* TODO: use phase2_fixup to disable SATA */
|
||||
|
||||
/* Causes coreboot to hang, so moved to stage1 code
|
||||
TODO: Fix vt8237s */
|
||||
static void sata_i_init(struct device *dev)
|
||||
{
|
||||
u8 reg;
|
||||
|
|
@ -100,12 +103,12 @@ struct device_operations vt8237r_sata = {
|
|||
{.pci = {.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_VT8237R_SATA}}},
|
||||
.constructor = default_device_constructor,
|
||||
.phase3_scan = 0,
|
||||
//.phase3_scan = 0,
|
||||
//.phase4_enable_disable = vt8237_enable,
|
||||
//.phase4_read_resources = pci_dev_read_resources,
|
||||
//.phase4_set_resources = pci_set_resources,
|
||||
//.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = sata_i_init,
|
||||
//.phase6_init = sata_i_init,
|
||||
};
|
||||
|
||||
struct device_operations vt8237s_sata = {
|
||||
|
|
@ -113,8 +116,7 @@ struct device_operations vt8237s_sata = {
|
|||
{.pci = {.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_VT8237S_SATA}}},
|
||||
.constructor = default_device_constructor,
|
||||
.phase2_fixup = 0,
|
||||
.phase3_scan = 0,
|
||||
//.phase3_scan = 0,
|
||||
//.phase4_enable_disable = vt8237_enable,
|
||||
//.phase4_read_resources = pci_dev_read_resources,
|
||||
//.phase4_set_resources = pci_set_resources,
|
||||
|
|
|
|||
|
|
@ -27,12 +27,13 @@
|
|||
#include <device/pci_ids.h>
|
||||
#include <spd.h>
|
||||
#include "vt8237.h"
|
||||
#include <config.h>
|
||||
|
||||
/* TODO List:
|
||||
* * Merge the rest of the functions from v2, except smbus_fixup which doesn't
|
||||
* seem to be necessary any more (?)
|
||||
* * Clean up vt8237_early_network_init.
|
||||
* Comments in code indicate that it's broken?
|
||||
* Comments in code indicate that it's broken?
|
||||
* * Figure out if the smbus actually needs to be reset after every transaction.
|
||||
*/
|
||||
|
||||
|
|
@ -189,6 +190,76 @@ void enable_smbus(u16 smbus_io_base)
|
|||
inb(smbus_io_base + SMBHSTCTL);
|
||||
}
|
||||
|
||||
/* The change from RAID to SATA in phase6 causes coreboot to lock up, so do it
|
||||
* as early as possible. Move back to stage2 later */
|
||||
static void sata_stage1(void)
|
||||
{
|
||||
u32 dev;
|
||||
u8 reg;
|
||||
|
||||
pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_SATA, &dev);
|
||||
|
||||
printk(BIOS_DEBUG, "Configuring VIA SATA controller\n");
|
||||
|
||||
/* Class IDE Disk */
|
||||
reg = pci_conf1_read_config8(dev, SATA_MISC_CTRL);
|
||||
reg &= 0x7f; /* Sub Class Write Protect off */
|
||||
pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg);
|
||||
|
||||
/* Change the device class to SATA from RAID. */
|
||||
pci_conf1_write_config8(dev, PCI_CLASS_DEVICE, 0x1);
|
||||
reg |= 0x80; /* Sub Class Write Protect on */
|
||||
pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg);
|
||||
}
|
||||
|
||||
void vt8237_stage1(u16 smbus_io_base)
|
||||
{
|
||||
u32 dev;
|
||||
u32 ide_dev;
|
||||
|
||||
printk(BIOS_DEBUG, "Doing vt8237r/s stage1 init\n");
|
||||
|
||||
pci_conf1_find_device(0x1106, 0x3227, &dev);
|
||||
pci_conf1_find_device(0x1106, 0x0571, &ide_dev);
|
||||
|
||||
/* Disable GP3 timer, or else the system reboots when it runs out */
|
||||
pci_conf1_write_config8(dev, 0x98, 0x00);
|
||||
|
||||
/* Change the ROM size mapping based on where CAR is located */
|
||||
#if (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xffc00000
|
||||
pci_conf1_write_config8(dev, 0x41, 0x7f);
|
||||
#elif (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xffe00000
|
||||
pci_conf1_write_config8(dev, 0x41, 0x70);
|
||||
#elif (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xfff00000
|
||||
pci_conf1_write_config8(dev, 0x41, 0x40);
|
||||
#endif
|
||||
|
||||
pci_conf1_write_config8(dev, 0x50, 0x80);//disable mc97
|
||||
pci_conf1_write_config8(dev, 0x51, 0x1f);
|
||||
pci_conf1_write_config8(dev, 0x58, 0x60);
|
||||
pci_conf1_write_config8(dev, 0x59, 0x80);
|
||||
pci_conf1_write_config8(dev, 0x5b, 0x08);
|
||||
|
||||
/* Make it respond to IO space */
|
||||
pci_conf1_write_config8(ide_dev, 0x04, 0x07);
|
||||
|
||||
/* Compatibility mode addresses */
|
||||
//pci_conf1_write_config32(ide_dev, 0x10, 0);
|
||||
//pci_conf1_write_config32(ide_dev, 0x14, 0);
|
||||
//pci_conf1_write_config32(ide_dev, 0x18, 0);
|
||||
//pci_conf1_write_config32(ide_dev, 0x1b, 0);
|
||||
|
||||
/* Native mode base address */
|
||||
//pci_conf1_write_config32(ide_dev, 0x20, BUS_MASTER_ADDR | 1);
|
||||
|
||||
pci_conf1_write_config8(ide_dev, 0x40, 0x3);//was 0x3
|
||||
pci_conf1_write_config8(ide_dev, 0x41, 0xf2);
|
||||
pci_conf1_write_config8(ide_dev, 0x42, 0x09);
|
||||
|
||||
sata_stage1();
|
||||
enable_smbus(smbus_io_base);
|
||||
}
|
||||
|
||||
/* TODO:
|
||||
* Magic numbers -> #defines
|
||||
* fix?
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@ struct vt8237_network_rom {
|
|||
} __attribute__ ((packed));
|
||||
|
||||
void enable_smbus(u16);
|
||||
void vt8237_stage1(u16);
|
||||
u8 smbus_read_byte(u16, u8, u16);
|
||||
void vt8237_enable(struct device *);
|
||||
|
||||
|
|
|
|||
|
|
@ -34,4 +34,6 @@
|
|||
#define VT1211_FIR 12 /* IRDA */
|
||||
#define VT1211_ROM 13 /* ROM control */
|
||||
|
||||
void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase);
|
||||
|
||||
#endif /* SUPERIO_VIA_VT1211_VT122_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue