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mb/asus: Add PRIME H610i-PLUS D4 (Alderlake/LGA1700)

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This port adds support for the ASUS PRIME H610i-PLUS D4, a Mini-ITX
LGA1700 motherboard with the H610 chipset. I have been using this
port on one of these boards as my primary workstation for around
the last month, and it generally works well apart from a lack of S3
sleep. I have not yet managed to figure out the issue with that,
and have been using suspend-to-disk instead.

This board is highly similar to the H610M-K ported by Mate Kukri in
#84243, and I have included the NCT6798D fan control setup from
that patchset with minimal modification.

Working:
- Console over onboard serial port
- PS/2 keyboard
- Port 80 POST codes over ASUS debug header
- All USB ports, including USB3 working, except front USB2
- All outputs (DP, HDMI, VGA) for iGPU
- M.2 slot
- PCIe WiFi card in WiFi slot
- Onboard Ethernet
- PCIe ASPM and clock power management for all devices
- x16 PCIe slot
- All SATA ports
- Hard drive indicator LED
- All audio including front panel
- Fan control
- ME disable with HAP bit in IFD
- HSPHY-in-FMAP when ME is disabled

Untested:
- CNVi WiFi card in WiFi slot
- Front USB2 ports (did not have an adapter on hand to test)
- Status LEDs in actual error states (they do show a normal status
normally)

Not working:
- S3 sleep

Change-Id: Ib2dd2916be06dc515863df85ecb06ec043a9bc6e
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Dodoid 2025-09-14 01:12:04 -04:00 • committed by Matt DeVillier
commit 67a3fb6abe
14 changed files with 1262 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

34
src/mainboard/asus/h610i-plus-d4/Kconfig Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config BOARD_ASUS_H610I_PLUS_D4
select BOARD_ROMSIZE_KB_16384
select DRIVERS_UART_8250IO
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT
select SOC_INTEL_ALDERLAKE_PCH_S
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SUPERIO_NUVOTON_NCT6791D
select USE_LEGACY_8254_TIMER
if BOARD_ASUS_H610I_PLUS_D4
config MAINBOARD_DIR
default "asus/h610i-plus-d4"
config MAINBOARD_PART_NUMBER
default "PRIME H610I-PLUS D4"
config MAINBOARD_VENDOR
default "ASUS"
config UART_FOR_CONSOLE
default 0
config USE_PM_ACPI_TIMER
default n
config CBFS_SIZE
default 0xB00000
endif

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src/mainboard/asus/h610i-plus-d4/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config BOARD_ASUS_H610I_PLUS_D4
bool "PRIME H610I-PLUS D4"

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src/mainboard/asus/h610i-plus-d4/Makefile.mk Normal file
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## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += bootblock.c
romstage-y += romstage_fsp_params.c
ramstage-y += mainboard.c

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src/mainboard/asus/h610i-plus-d4/board_info.txt Normal file
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Category: desktop
Board URL: https://www.asus.com/us/motherboards-components/motherboards/prime/prime-h610i-plus-d4/
ROM IC: W25Q128JVSQ
ROM package: SOIC-8
ROM socketed: no
Flashrom support: yes
Release year: 2022

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src/mainboard/asus/h610i-plus-d4/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <superio/nuvoton/common/nuvoton.h>
// This board actually uses an NCT6798D, but NCT6791D seems compatible
#include <superio/nuvoton/nct6791d/nct6791d.h>
#define SERIAL_DEV PNP_DEV(0x2e, NCT6791D_SP1)
#define P80_UART_DEV PNP_DEV(0x2e, NCT6791D_PORT80)
#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI)
#define WDTMEM_DEV PNP_DEV(0x2e, NCT6791D_BCLK_WDT2_WDTMEM)
#define CIRWUP_DEV PNP_DEV(0x2e, NCT6791D_CIRWUP)
#define DS_DEV PNP_DEV(0x2e, NCT6791D_DS)
void bootblock_mainboard_early_init(void)
{
// Start configuring the SIO
nuvoton_pnp_enter_conf_state(P80_UART_DEV);
// Replicate vendor global config LDN
pnp_write_config(P80_UART_DEV, 0x07, 0x0b);
pnp_write_config(P80_UART_DEV, 0x10, 0xcf);
pnp_write_config(P80_UART_DEV, 0x11, 0xc3);
pnp_write_config(P80_UART_DEV, 0x13, 0x0c);
pnp_write_config(P80_UART_DEV, 0x14, 0xb8);
pnp_write_config(P80_UART_DEV, 0x1a, 0x10);
pnp_write_config(P80_UART_DEV, 0x1b, 0x00);
pnp_write_config(P80_UART_DEV, 0x1c, 0x10);
pnp_write_config(P80_UART_DEV, 0x24, 0x00);
pnp_write_config(P80_UART_DEV, 0x27, 0x00);
pnp_write_config(P80_UART_DEV, 0x2a, 0x58);
pnp_write_config(P80_UART_DEV, 0x2b, 0x02); // Enable the Port 80 UART
pnp_write_config(P80_UART_DEV, 0x2c, 0x0a);
pnp_write_config(P80_UART_DEV, 0x2d, 0x30);
// Configure the ACPI LD to match stock
pnp_set_logical_device(ACPI_DEV);
pnp_write_config(ACPI_DEV, 0xe5, 0x02);
pnp_write_config(ACPI_DEV, 0xe6, 0x1a);
pnp_write_config(ACPI_DEV, 0xf2, 0x5d);
// Configure BCLK/WDT2/WDTMEM
pnp_set_logical_device(WDTMEM_DEV);
pnp_write_config(WDTMEM_DEV, 0xe2, 0x03);
pnp_write_config(WDTMEM_DEV, 0xf0, 0x80);
// Configure CIR Wakeup
pnp_set_logical_device(CIRWUP_DEV);
pnp_write_config(CIRWUP_DEV, 0x30, 0x00);
// Configure Deep Sleep
pnp_set_logical_device(DS_DEV);
pnp_write_config(DS_DEV, 0x30, 0xa0); // Disable deep S5
nuvoton_pnp_exit_conf_state(ACPI_DEV);
// Enable serial port
if (CONFIG(CONSOLE_SERIAL))
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}

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src/mainboard/asus/h610i-plus-d4/data.vbt Normal file
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src/mainboard/asus/h610i-plus-d4/devicetree.cb Normal file
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chip soc/intel/alderlake
register "eist_enable" = "true"
# Sagv Configuration
register "sagv" = "SaGv_Enabled"
register "RMT" = "0"
register "enable_c6dram" = "1"
register "pmc_gpe0_dw0" = "GPP_J"
register "pmc_gpe0_dw1" = "GPP_VPGIO"
register "pmc_gpe0_dw2" = "GPD"
device domain 0 on
# USB Configuration - copied from ms7d25, all ports work but possibly excessive
device ref xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_SHORT(OC2),
[1] = USB2_PORT_SHORT(OC1),
[2] = USB2_PORT_SHORT(OC0),
[3] = USB2_PORT_LONG(OC0),
[4] = USB2_PORT_SHORT(OC3),
[5] = USB2_PORT_LONG(OC3),
[6] = USB2_PORT_LONG(OC7),
[7] = USB2_PORT_LONG(OC0),
[8] = USB2_PORT_LONG(OC2),
[9] = USB2_PORT_LONG(OC7),
[10] = USB2_PORT_SHORT(OC0),
[11] = USB2_PORT_SHORT(OC0),
[12] = USB2_PORT_SHORT(OC0),
[13] = USB2_PORT_SHORT(OC0),
[14] = USB2_PORT_EMPTY,
[15] = USB2_PORT_EMPTY,
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC2),
[1] = USB3_PORT_DEFAULT(OC2),
[2] = USB3_PORT_DEFAULT(OC3),
[3] = USB3_PORT_DEFAULT(OC0),
[4] = USB3_PORT_DEFAULT(OC7),
[5] = USB3_PORT_DEFAULT(OC7),
[6] = USB3_PORT_DEFAULT(OC2),
[7] = USB3_PORT_DEFAULT(OC2),
[8] = USB3_PORT_DEFAULT(OC0),
[9] = USB3_PORT_EMPTY,
}"
end
device ref sata on
register "sata_salp_support" = "1"
register "sata_ports_enable" = "{
[4] = 1,
[5] = 1,
[6] = 1,
[7] = 1,
}"
register "sata_ports_dev_slp" = "{
[4] = 0,
[5] = 0,
[6] = 0,
[7] = 0,
}"
end
# HDMI on port B
register "ddi_portB_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_2] = DDI_ENABLE_HPD,
[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_4] = DDI_ENABLE_HPD,
}"
register "hybrid_storage_mode" = "true"
register "dmi_power_optimize_disable" = "true"
# FIVR configuration
register "fivr_rfi_frequency" = "1394"
register "fivr_spread_spectrum" = "FIVR_SS_1_5"
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
}"
# PCIe x16 Slot
# PEG10 (dGPU)
device ref pcie5_0 on
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
smbios_slot_desc "SlotTypePciExpressGen4x16" "SlotLengthLong"
"PCI_E1" "SlotDataBusWidth16X"
end
device ref igpu on end
device ref crashlog off end
device ref cnvi_wifi on
# Enable CNVi BT
register "cnvi_bt_core" = "true"
register "cnvi_bt_audio_offload" = "false"
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "enable_cnvi_ddr_rfim" = "true"
device generic 0 on end
end
end
# HECI to ME
device ref heci1 on end
# M.2 Slot
device ref pcie_rp1 on
register "pch_pcie_rp[PCH_RP(1)]" = "{
.clk_src = 11,
.clk_req = 11,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
"M2_1" "SlotDataBusWidth4X"
end
# Onboard LAN
device ref pcie_rp5 on
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
# WLAN (when not using CNVi)
device ref pcie_rp6 on
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 12,
.clk_req = 12,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
"M2_1" "SlotDataBusWidth4X"
end
device ref pch_espi on
# HWM I/O decode range
register "gen1_dec" = "0x007c0281"
chip superio/nuvoton/nct6791d
device pnp 2e.1 off end # Parallel port (this line needed for super i/o init to work)
device pnp 2e.2 on # UART A
io 0x60 = 0x03f8
irq 0x70 = 4
# Pin 121 is PECI
irq 0x2c = 0
end
device pnp 2e.5 on # PS/2 KBC
io 0x60 = 0x0060
io 0x62 = 0x0064
irq 0x70 = 1
irq 0x72 = 12
irq 0xf0 = 0x82
end
device pnp 2e.b on # HWM
io 0x60 = 0x0290
io 0x62 = 0x0b00
io 0x64 = 0x0a00
irq 0xf0 = 0xfe
end
end
end
device ref p2sb on end
device ref hda on
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_sdi_enable[0]" = "1"
register "pch_hda_dsp_enable" = "0"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "1"
end
device ref smbus on end
end
end

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src/mainboard/asus/h610i-plus-d4/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0) {
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/alderlake/acpi/southbridge.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
}

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src/mainboard/asus/h610i-plus-d4/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef CFG_GPIO_H
#define CFG_GPIO_H
#include <gpio.h>
/* Pad configuration was generated automatically using intelp2m 2.5-149f0c750c */
static const struct pad_config gpio_table[] = {
/* ------- GPIO Community 0 ------- */
/* ------- GPIO Group GPP_I ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I7, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I18, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I19, NONE, RSMRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I20, NONE, RSMRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, RSMRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Group GPP_R ------- */
_PAD_CFG_STRUCT(GPP_R0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_R1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_R2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_R3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_R4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R8, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R9, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R10, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R11, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R12, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R13, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R14, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R15, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_R16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0),
_PAD_CFG_STRUCT(GPP_R17, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_R18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0),
_PAD_CFG_STRUCT(GPP_R19, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_R20, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_R21, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Group GPP_J ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_J0, NONE, RSMRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPO(GPP_J7, 0, PLTRST),
PAD_CFG_GPI_TRIG_OWN(GPP_J8, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_J9, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Group vGPIO ------- */
/* ------- GPIO Group vGPIO_0 ------- */
/* ------- GPIO Community 1 ------- */
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPO(GPP_B3, 1, PLTRST),
PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)),
PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
_PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPO(GPP_B20, 0, PLTRST),
_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, 0),
PAD_CFG_GPO(GPP_B22, 0, PLTRST),
_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
/* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, 0),
PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Group GPP_H ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_H6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H13, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H14, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_H16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, 0),
PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, RSMRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, RSMRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, RSMRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Community 2 ------- */
/* ------- GPIO Group GPD ------- */
PAD_CFG_GPI_TRIG_OWN(GPD0, NONE, PWROK, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, PWROK, OFF, ACPI), /* GPIO */
PAD_CFG_NF(GPD2, NONE, PWROK, NF1), /* LAN_WAKE# */
PAD_CFG_NF(GPD3, NONE, PWROK, NF1), /* PWRBTN# */
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */
PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, PWROK, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PWROK, OFF, ACPI), /* GPIO */
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */
PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, PWROK, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPD10, 0, PWROK), /* GPIO */
PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPD12, NONE, PWROK, OFF, ACPI), /* GPIO */
/* ------- GPIO Community 3 ------- */
/* ------- GPIO Group SPI ------- */
/* ------- GPIO Group GPP_A ------- */
_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)),
_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_A8, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_A9, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Group GPP_C ------- */
_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
PAD_CFG_GPI_TRIG_OWN(GPP_C3, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_C4, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
PAD_CFG_GPO(GPP_C6, 0, PLTRST),
PAD_CFG_GPI_TRIG_OWN(GPP_C7, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, RSMRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, RSMRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_C20, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Group vGPIO_3 ------- */
/* ------- GPIO Community 4 ------- */
/* ------- GPIO Group GPP_S ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_S0, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_S1, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_S2, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_S3, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_S4, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_S5, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_S6, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_S7, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Group GPP_E ------- */
_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, 0),
PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI),
PAD_NC(GPP_E3, NONE),
_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPO(GPP_E19, 0, PLTRST),
PAD_CFG_GPI_TRIG_OWN(GPP_E20, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_E21, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Group GPP_K ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_K2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_K6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
_PAD_CFG_STRUCT(GPP_K7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)),
PAD_CFG_GPO(GPP_K8, 1, PLTRST),
_PAD_CFG_STRUCT(GPP_K9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_K10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
PAD_CFG_GPI_TRIG_OWN(GPP_K11, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F19, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F20, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, 0),
PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Community 5 ------- */
/* ------- GPIO Group GPP_D ------- */
_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF3) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
_PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI),
_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, RSMRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI),
/* ------- GPIO Group JTAG ------- */
/* ------- GPIO Group CPU ------- */
};
/* PCIe CLK REQs as per devicetree.cb */
static const struct pad_config clkreq_disabled_table[] = {
/* GPP_D0 - SRCCLKREQ0# */
PAD_NC(GPP_D0, NONE),
/* GPP_H6 - SRCCLKREQ4# */
PAD_NC(GPP_D11, NONE),
/* GPP_H6 - SRCCLKREQ11# */
PAD_NC(GPP_H5, NONE),
/* GPP_H6 - SRCCLKREQ12# */
PAD_NC(GPP_H6, NONE),
/* CPU PCIe CLKREQ virtual wire message buses */
_PAD_CFG_STRUCT(VGPIO_PCIE_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_1, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_2, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_3, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_6, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_7, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_8, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_9, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_34, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_35, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_36, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_38, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_39, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_40, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_41, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_42, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_43, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_44, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_45, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_46, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_47, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_72, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_73, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_75, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_48, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_49, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_50, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_51, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_52, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_53, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_54, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_55, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_56, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_57, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_58, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_59, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_60, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_61, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_62, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_63, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_76, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_77, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
_PAD_CFG_STRUCT(VGPIO_PCIE_79, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
};
#endif /* CFG_GPIO_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10ec0897, // Vendor/Device ID: Realtek ALC897
0x10438803, // Subsystem ID
15,
AZALIA_SUBVENDOR(0, 0x10438803),
AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x12, 0x40330040), // does not describe a jack or internal device
AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR,
AZALIA_LINE_OUT,
AZALIA_STEREO_MONO_1_8,
AZALIA_GREEN,
AZALIA_JACK_PRESENCE_DETECT,
1, 0
)),
AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR,
AZALIA_LINE_IN,
AZALIA_STEREO_MONO_1_8,
AZALIA_BLUE,
AZALIA_JACK_PRESENCE_DETECT,
3, 15
)),
AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR,
AZALIA_MIC_IN,
AZALIA_STEREO_MONO_1_8,
AZALIA_PINK,
AZALIA_JACK_PRESENCE_DETECT,
3, 0
)),
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT,
AZALIA_MIC_IN,
AZALIA_STEREO_MONO_1_8,
AZALIA_PINK,
AZALIA_JACK_PRESENCE_DETECT,
4, 0
)),
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC(
AZALIA_INTEGRATED,
AZALIA_INTERNAL,
AZALIA_SPEAKER,
AZALIA_OTHER_ANALOG,
AZALIA_COLOR_UNKNOWN,
AZALIA_NO_JACK_PRESENCE_DETECT,
1, 15
)),
AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT,
AZALIA_HP_OUT,
AZALIA_STEREO_MONO_1_8,
AZALIA_GREEN,
AZALIA_JACK_PRESENCE_DETECT,
2, 0
)),
AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1d, 0x4048ee29), // does not describe a jack or internal device
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
0x80862815, // Vendor/Device ID: Intel Alderlake HDMI
0x80860101, // Subsystem ID
10,
AZALIA_SUBVENDOR(2, 0x80860101),
AZALIA_PIN_CFG(2, 0x04, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_DIGITAL_DISPLAY,
AZALIA_DIGITAL_OTHER_OUT,
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
1, 0
)),
AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_DIGITAL_DISPLAY,
AZALIA_DIGITAL_OTHER_OUT,
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
1, 0
)),
AZALIA_PIN_CFG(2, 0x08, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_DIGITAL_DISPLAY,
AZALIA_DIGITAL_OTHER_OUT,
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
1, 0
)),
AZALIA_PIN_CFG(2, 0x0a, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_DIGITAL_DISPLAY,
AZALIA_DIGITAL_OTHER_OUT,
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
1, 0
)),
AZALIA_PIN_CFG(2, 0x0b, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_DIGITAL_DISPLAY,
AZALIA_DIGITAL_OTHER_OUT,
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
1, 0
)),
AZALIA_PIN_CFG(2, 0x0c, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_DIGITAL_DISPLAY,
AZALIA_DIGITAL_OTHER_OUT,
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
1, 0
)),
AZALIA_PIN_CFG(2, 0x0d, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_DIGITAL_DISPLAY,
AZALIA_DIGITAL_OTHER_OUT,
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
1, 0
)),
AZALIA_PIN_CFG(2, 0x0e, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_DIGITAL_DISPLAY,
AZALIA_DIGITAL_OTHER_OUT,
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
1, 0
)),
AZALIA_PIN_CFG(2, 0x0f, AZALIA_PIN_DESC(
AZALIA_JACK,
AZALIA_DIGITAL_DISPLAY,
AZALIA_DIGITAL_OTHER_OUT,
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
1, 0
)),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <device/device.h>
#include <identity.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <smbios.h>
#include <string.h>
#include <bootstate.h>
#include <superio/nuvoton/common/hwm.h>
// This is the base address of the HWM registers (set in the device tree)
#define HWM_IOBASE 0x290
// The registers below are in a separate bank for each fan
// On the H610I-PLUS and H610M-K only SYSFAN and CPUFAN are wired up
#define BANK_SYSFAN 1
#define BANK_CPUFAN 2
#define FAN_SOURCE 0x00 // Fan control temperature source
# define FAN_SOURCE_PECI0 0x10 // PECI Agent 0
# define FAN_SOURCE_PECI0_CAL 0x1c // PECI Agent 0 Calibration
#define FAN_MODE_TEMP_TOLERANCE 0x02 // [7:4] = mode [2:0] temperature tolerance
# define FAN_MODE_SFIV 4 // SmartFan IV
#define FAN_STEP_UP_TIME 0x03 // In 0.1 sec
#define FAN_STEP_DOWN_TIME 0x04 // In 0.1 sec
#define FAN_DUTY_PER_STEP 0x66 // [7:4] step up val [3:0] step down val
#define FAN_TEMP(i) (0x21 + (i)) // Temperature points on the curve (4 points)
#define FAN_DUTY(i) (0x27 + (i)) // Corresponding duty for each temperature point
#define FAN_CRIT_TEMP 0x35 // Critical temperature
#define FAN_CRIT_DUTY_EN 0x36 // Use critical duty (or default to 255)
#define FAN_CRIT_DUTY 0x37 // Critical duty
#define FAN_CRIT_TEMP_TOLERANCE 0x38 // Critical temperature tolerance
struct nct_fan {
const char *name;
uint8_t bank;
// Temperature source
uint8_t source;
// Temperature x duty cycle curve points
uint8_t temp[4];
uint8_t duty[4];
// Temperature tolerance
uint8_t temp_tolerance;
// Step up and down smoothing
uint8_t step_up_time;
uint8_t step_down_time;
uint8_t duty_per_step_up;
uint8_t duty_per_step_down;
// Critical mode
uint8_t crit_temp;
uint8_t crit_duty_en;
uint8_t crit_duty;
uint8_t crit_temp_tolerance;
};
#define PERCENT_TO_DUTY(perc) ((perc) * 255 / 100)
// These fan curves have been adjusted from Mate Kukri's original values (for his i3-12100), and work well with my i7-12700
static const struct nct_fan NCT_FANS[] = {
{
.name = "SYSFAN",
.bank = BANK_SYSFAN,
.source = FAN_SOURCE_PECI0,
.temp = {40, 60, 75, 90},
.duty = {PERCENT_TO_DUTY(20), PERCENT_TO_DUTY(40), PERCENT_TO_DUTY(70), PERCENT_TO_DUTY(100)},
.crit_temp = 100,
.crit_duty_en = 1,
.crit_duty = 255,
.crit_temp_tolerance = 2,
},
{
.name = "CPUFAN",
.bank = BANK_CPUFAN,
.source = FAN_SOURCE_PECI0,
.temp = {40, 60, 75, 90},
.duty = {PERCENT_TO_DUTY(20), PERCENT_TO_DUTY(40), PERCENT_TO_DUTY(70), PERCENT_TO_DUTY(100)},
.crit_temp = 100,
.crit_duty_en = 1,
.crit_duty = 255,
.crit_temp_tolerance = 2,
},
};
void mainboard_fill_fadt(acpi_fadt_t *fadt)
{
fadt->preferred_pm_profile = PM_DESKTOP;
fadt->iapc_boot_arch |= ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
}
static void mainboard_init(void *chip_info)
{
}
static void mainboard_enable(struct device *dev)
{
}
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
uint8_t aspm, aspm_l1;
/* ASPM L1 sub-states require CLKREQ, so CLK_PM should be enabled as well */
if (CONFIG(PCIEXP_L1_SUB_STATE) && CONFIG(PCIEXP_CLK_PM))
aspm_l1 = 2; // 2 - L1.1 and L1.2
else
aspm_l1 = 0;
if (CONFIG(PCIEXP_ASPM)) {
aspm = CONFIG(PCIEXP_L1_SUB_STATE) ? 3 : 1; // 3 - L0sL1, 1 - L0s
} else {
aspm = 0;
aspm_l1 = 0;
}
memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm));
memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm));
memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating));
memset(params->CpuPciePowerGating, 0, sizeof(params->CpuPciePowerGating));
params->UsbPdoProgramming = 1;
params->CpuPcieFiaProgramming = 1;
params->PcieRpFunctionSwap = 0;
params->CpuPcieRpFunctionSwap = 0;
params->PchLegacyIoLowLatency = 1;
params->PchDmiAspmCtrl = 0;
params->CpuPcieRpPmSci[2] = 1; // PCI_E1
params->PcieRpPmSci[1] = 1; // M2_1
params->PcieRpPmSci[5] = 1; // Ethernet
params->PcieRpPmSci[6] = 1; // WiFi
params->PcieRpMaxPayload[0] = 1; // PCI_E2
params->PcieRpMaxPayload[1] = 1; // M2_1
params->PcieRpMaxPayload[5] = 1; // Ethernet
params->PcieRpMaxPayload[6] = 1; // WiFi
params->CpuPcieRpTransmitterHalfSwing[2] = 1; // PCI_E1
params->PcieRpTransmitterHalfSwing[1] = 1; // M2_1
params->PcieRpTransmitterHalfSwing[5] = 1; // Ethernet
params->PcieRpTransmitterHalfSwing[6] = 1; // WiFi
params->CpuPcieRpEnableCpm[2] = CONFIG(PCIEXP_CLK_PM); // PCI_E1
params->PcieRpEnableCpm[1] = CONFIG(PCIEXP_CLK_PM); // M2_1
params->PcieRpEnableCpm[5] = CONFIG(PCIEXP_CLK_PM); // Ethernet
params->PcieRpEnableCpm[6] = CONFIG(PCIEXP_CLK_PM); // WiFi
params->CpuPcieRpL1Substates[2] = aspm_l1; // PCI_E1
params->PcieRpL1Substates[1] = aspm_l1; // M2_1
params->PcieRpL1Substates[5] = aspm_l1; // Ethernet
params->PcieRpL1Substates[6] = aspm_l1; // WiFi
params->CpuPcieRpAspm[2] = aspm; // PCI_E1
params->PcieRpAspm[1] = aspm; // M2_1
params->PcieRpAspm[5] = aspm; // Ethernet
params->PcieRpAspm[6] = aspm; // WiFi
params->PcieRpAcsEnabled[1] = 1; // M2_1
params->PcieRpAcsEnabled[5] = 1; // Ethernet
params->PcieRpAcsEnabled[6] = 1; // WiFi
params->CpuPcieClockGating[2] = CONFIG(PCIEXP_CLK_PM);
params->CpuPciePowerGating[2] = CONFIG(PCIEXP_CLK_PM);
params->CpuPcieRpPeerToPeerMode[2] = 1;
params->CpuPcieRpMaxPayload[2] = 2; // 512B
params->CpuPcieRpAcsEnabled[2] = 1;
params->SataLedEnable = 1;
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};
static void nct6798d_hwm_init(void *arg)
{
printk(BIOS_DEBUG, "NCT6798D HWM configuration\n");
// Setup PECI
// Devicetree must set pin 121 to PECI mode first
nuvoton_hwm_select_bank(HWM_IOBASE, 7);
pnp_write_hwm5_index(HWM_IOBASE, 1, 0x85);
pnp_write_hwm5_index(HWM_IOBASE, 2, 0x02);
pnp_write_hwm5_index(HWM_IOBASE, 3, 0x10);
pnp_write_hwm5_index(HWM_IOBASE, 4, 0x00);
pnp_write_hwm5_index(HWM_IOBASE, 9, 0x64);
// Enable PECI temp reading
nuvoton_hwm_select_bank(HWM_IOBASE, 0);
pnp_write_hwm5_index(HWM_IOBASE, 0xae, 1);
// Program PECI Agent 0 Calibration
nuvoton_hwm_select_bank(HWM_IOBASE, 4);
pnp_write_hwm5_index(HWM_IOBASE, 0xf8, 0x50);
pnp_write_hwm5_index(HWM_IOBASE, 0xfa, 0x51);
// Program fan control profiles
for (const struct nct_fan *fan = NCT_FANS; fan < NCT_FANS + ARRAY_SIZE(NCT_FANS); ++fan) {
printk(BIOS_DEBUG, "Configuring NCT6798D fan %s\n", fan->name);
nuvoton_hwm_select_bank(HWM_IOBASE, fan->bank);
pnp_write_hwm5_index(HWM_IOBASE, FAN_SOURCE, fan->source);
for (size_t i = 0; i < 4; ++i)
pnp_write_hwm5_index(HWM_IOBASE, FAN_TEMP(i), fan->temp[i]);
for (size_t i = 0; i < 4; ++i)
pnp_write_hwm5_index(HWM_IOBASE, FAN_DUTY(i), fan->duty[i]);
pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_TEMP, fan->crit_temp);
pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_DUTY_EN, fan->crit_duty_en);
pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_DUTY, fan->crit_duty);
pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_TEMP_TOLERANCE, fan->crit_temp_tolerance);
pnp_write_hwm5_index(HWM_IOBASE, FAN_STEP_UP_TIME, fan->step_up_time);
pnp_write_hwm5_index(HWM_IOBASE, FAN_STEP_DOWN_TIME, fan->step_down_time);
pnp_write_hwm5_index(HWM_IOBASE, FAN_DUTY_PER_STEP, fan->duty_per_step_up << 4 | fan->duty_per_step_down);
// There are other modes supported by hardware, but always use SmartFan IV mode here
pnp_write_hwm5_index(HWM_IOBASE, FAN_MODE_TEMP_TOLERANCE, (FAN_MODE_SFIV << 4) | fan->temp_tolerance);
}
}
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, nct6798d_hwm_init, NULL);

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <fsp/api.h>
#include <soc/romstage.h>
#include <soc/meminit.h>
#include <string.h>
#include "gpio.h"
#define FSP_CLK_NOTUSED 0xFF
#define FSP_CLK_FREE_RUNNING 0x80
static const struct mb_cfg ddr4_mem_config = {
.type = MEM_TYPE_DDR4,
.UserBd = BOARD_TYPE_DESKTOP_1DPC,
.ddr_config = {
.dq_pins_interleaved = true,
},
};
static const struct mem_spd dimm_module_spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = {
.addr_dimm[0] = 0x50,
},
[1] = {
.addr_dimm[0] = 0x52,
},
},
};
static void disable_pcie_clock_requests(FSP_M_CONFIG *m_cfg)
{
memset(m_cfg->PcieClkSrcUsage, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcUsage));
memset(m_cfg->PcieClkSrcClkReq, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcClkReq));
/* PCIe CLK SRCes as per devicetree.cb */
m_cfg->PcieClkSrcUsage[0] = FSP_CLK_FREE_RUNNING;
m_cfg->PcieClkSrcUsage[4] = FSP_CLK_FREE_RUNNING;
m_cfg->PcieClkSrcUsage[11] = FSP_CLK_FREE_RUNNING;
m_cfg->PcieClkSrcUsage[12] = FSP_CLK_FREE_RUNNING;
gpio_configure_pads(clkreq_disabled_table, ARRAY_SIZE(clkreq_disabled_table));
}
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = CONFIG(PCIEXP_CLK_PM);
memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = CONFIG(PCIEXP_CLK_PM);
memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = CONFIG(PCIEXP_CLK_PM);
memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented
memupd->FspmConfig.DmiAspm = 0;
memupd->FspmConfig.DmiAspmCtrl = 0;
memupd->FspmConfig.SkipExtGfxScan = 0;
memupd->FspmConfig.PchHdaSdiEnable[0] = 1;
memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false);
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
if (!CONFIG(PCIEXP_CLK_PM))
disable_pcie_clock_requests(&memupd->FspmConfig);
}