From 6781f458eec800e6be897cc0b82f0c644d998991 Mon Sep 17 00:00:00 2001 From: Luca Lai Date: Sat, 23 Aug 2025 00:06:30 +0800 Subject: [PATCH] mb/google/trulo/var/pujjolo: Enable fivr settings Add fivr related setting based on schematics 500E_S3A0_TWL_MB_FVT_20250527.pdf BUG=b:437881361 TEST=Build and boot to OS, check suspend funtion work fine using suspend_stress_test -c 5 command. Change-Id: I6c7f2807cc6a9c7c82e28d26205b33d068792522 Signed-off-by: Luca Lai Reviewed-on: https://review.coreboot.org/c/coreboot/+/88907 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Eric Lai --- src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb index 7e009e001f..9b88e4b54a 100644 --- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb @@ -91,6 +91,10 @@ chip soc/intel/alderlake register "pch_hda_sdi_enable[0]" = "true" register "pch_hda_sdi_enable[1]" = "true" + # Configure external V1P05/Vnn/VnnSx Rails for Pujjolo + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" # Intel Common SoC Config #+-------------------+---------------------------+