erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: soc/intel/apollolake: remove southbridge_clear_smi_status()

Browse source 
The southbridge_clear_smi_status() is not used. Remove it.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ibe0c80606c212aec090632bf069ddb3442f18270
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0edf5dc331
Original-Change-Id: Ia358c6aca93630753ac4b59b6fc86b1ea1eb9ca6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19599
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/498351
This commit is contained in:
Aaron Durbin 2017-05-05 15:52:48 -05:00 • committed by chrome-bot
commit 674d6bba56
2 changed files with 0 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/soc/intel/apollolake/include/soc/smm.h
View file

@ -22,9 +22,6 @@
#include <soc/gpio.h>
#include <fsp/memmap.h>
/* These helpers are for performing SMM relocation. */
void southbridge_clear_smi_status(void);
/*
* The initialization of the southbridge is split into 2 compoments. One is
* for clearing the state in the SMM registers. The other is for enabling

12
src/soc/intel/apollolake/smi.c
View file

@ -55,18 +55,6 @@ void southbridge_smm_enable_smi(void)
enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN);
}
void southbridge_clear_smi_status(void)
{
/* Clear SMI status */
clear_smi_status();
/* Clear PM1 status */
clear_pm1_status();
/* Set EOS bit so other SMIs can occur. */
enable_smi(EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
/*