Exynos5420: ddr3: fine tuning the DDR3 timing values

Browse source

Fine tuning DDR timings value for better stability

* Changed Data Driver Strength from 34 ohms to 30 ohms, expected to
  enhance signal integrity.
* Changed DQ signal from 0xf to 0x1f000f, to keep default value safe.
* Changed mrs[2] and added new mrs direct command for setting WL/RL
  without resetting DLL.
* Added explicit reset value write in phy_con0 instead of just setting
  a bit, to ensure that reset happens.
* Added DREX automatic control for ctrl_pd in none read memory state.

This is ported from: https://gerrit.chromium.org/gerrit/61405
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
BRANCH=none
TEST=booted on pit, suspend_stress_test --memory_check -c10 passed

Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1
Reviewed-on: https://chromium-review.googlesource.com/66995
Reviewed-by: ron minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>

...

This commit is contained in:

David Hendricks 2013-08-26 15:12:12 -07:00 • committed by chrome-internal-fetch

parent ec34b711c6

commit 667458cfb3

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

Diff content is not available