diff --git a/Rules.make b/Rules.make
index d44ac3ee91..f51a01ce60 100644
--- a/Rules.make
+++ b/Rules.make
@@ -27,13 +27,17 @@ $(obj)/mainboard/$(MAINBOARDDIR)/statictree.o: $(obj)/mainboard/$(MAINBOARDDIR)/
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) $(COREBOOTINCLUDE) -c -o $@ $<
 
+# Create a tmp file so that if the dtc fails we don't end up with a 
+# half-correct statictree.[ch]
 $(obj)/mainboard/$(MAINBOARDDIR)/statictree.c: $(src)/mainboard/$(MAINBOARDDIR)/dts $(obj)/util/dtc/dtc
 	$(Q)printf "  DTC     $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(obj)/util/dtc/dtc -O lb mainboard/$(MAINBOARDDIR)/dts > $@
+	$(Q)$(obj)/util/dtc/dtc -O lb mainboard/$(MAINBOARDDIR)/dts > /tmp/statictree.c.$$
+	$(Q)mv /tmp/statictree.c.$$ $@
 
 $(obj)/statictree.h: $(src)/mainboard/$(MAINBOARDDIR)/dts $(obj)/util/dtc/dtc
 	$(Q)printf "  DTC     $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(obj)/util/dtc/dtc -O lbh mainboard/$(MAINBOARDDIR)/dts > $@
+	$(Q)$(obj)/util/dtc/dtc -O lbh mainboard/$(MAINBOARDDIR)/dts > /tmp/statictree.h.$$
+	$(Q)mv /tmp/statictree.h.$$ $@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c: $(obj)/util/options/build_opt_tbl $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout
 	$(Q)printf "  OPTIONS $(subst $(shell pwd)/,,$(@))\n"
@@ -84,4 +88,3 @@ $(obj)/southbridge/%.o: $(src)/southbridge/%.c $(obj)/statictree.h
 	$(Q)mkdir -p $(dir $@)
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
-
diff --git a/mainboard/amd/dbm690t/Makefile b/mainboard/amd/dbm690t/Makefile
index 976aeb4828..96d438ef59 100644
--- a/mainboard/amd/dbm690t/Makefile
+++ b/mainboard/amd/dbm690t/Makefile
@@ -22,18 +22,17 @@
 			
 STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
 			$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
-			$(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
 			$(src)/arch/x86/stage1_mtrr.c \
 			$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
 			$(src)/arch/x86/amd/model_fxx/stage1.c \
 			$(src)/northbridge/amd/k8/get_nodes.c \
-			$(src)/northbridge/amd/k8/coherent_ht.c \
 			$(src)/northbridge/amd/k8/libstage1.c \
 
 INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/amd/k8/raminit.c \
 			$(src)/northbridge/amd/k8/dqs.c \
 			$(src)/northbridge/amd/k8/reset_test.c \
+			$(src)/northbridge/amd/k8/coherent_ht.c \
 			$(src)/northbridge/amd/k8/incoherent_ht.c \
 			$(src)/arch/x86/pci_ops_conf1.c \
 			$(src)/arch/x86/stage1_mtrr.c \