soc/intel/apl: Move cpu cluster to chipset.cb

Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-02-01 08:02:23 +01:00 · 2023-02-01 08:02:23 +01:00 · 64e2ecb36f
commit 64e2ecb36f
parent a10a86d2bc
24 changed files with 2 additions and 39 deletions
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@ -1,5 +1,4 @@
 chip soc/intel/apollolake
-	device cpu_cluster 0 on end

 	register "pcie_rp_clkreq_pin[2]" = "3"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
 	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
 	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
 	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
 	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
 	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@ -7,8 +7,6 @@ chip soc/intel/apollolake
 	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
 	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"

-	device cpu_cluster 0 on end
-
 	device domain 0 on
 		device pci 00.0 on end	# - Host Bridge
 		device pci 00.1 on end	# - DPTF
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
 	# Disable unused clkreq of PCIe root ports
 	register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@ -7,8 +7,6 @@ chip soc/intel/apollolake
 	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
 	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"

-	device cpu_cluster 0 on end
-
 	device domain 0 on
 		device pci 00.0 on end	# - Host Bridge
 		device pci 00.1 on end	# - DPTF
--- a/src/mainboard/intel/minnow3/devicetree.cb
+++ b/src/mainboard/intel/minnow3/devicetree.cb
@ -7,8 +7,6 @@ chip soc/intel/apollolake
 	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
 	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"

-	device cpu_cluster 0 on end
-
 	device domain 0 on
 		device pci 00.0 on end	# - Host Bridge
 		device pci 00.1 on end	# - DPTF
--- a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb
+++ b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb
@ -2,8 +2,6 @@

 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	# Override USB port configuration
 	register "usb_config_override" = "1"
 	# USB 2.0
--- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb
+++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb
@ -5,7 +5,6 @@ chip soc/intel/apollolake
 	register "enable_vtd" = "1"
 	register "dptf_enable" = "1"

-	device cpu_cluster 0 on end
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 00.1 on  end # DPTF
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "sci_irq" = "SCIS_IRQ10"

 	# EMMC TX DATA Delay 1
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "sci_irq" = "SCIS_IRQ10"

 	# EMMC TX DATA Delay 1
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "sci_irq" = "SCIS_IRQ10"

 	# EMMC TX DATA Delay 1
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "sci_irq" = "SCIS_IRQ10"

 	# EMMC TX DATA Delay 1
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "sci_irq" = "SCIS_IRQ10"

 	# EMMC TX DATA Delay 1
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "sci_irq" = "SCIS_IRQ10"

 	# 0:HS400(Default), 1:HS200, 2:DDR50
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb
@ -1,7 +1,5 @@
 chip soc/intel/apollolake

-	device cpu_cluster 0 on end
-
 	register "sci_irq" = "SCIS_IRQ10"

 	# EMMC TX DATA Delay 1
--- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
@ -1,5 +1,4 @@
 chip soc/intel/apollolake
-	device cpu_cluster 0 on end

 	# Graphics
 	# TODO:
--- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
@ -1,5 +1,4 @@
 chip soc/intel/apollolake
-	device cpu_cluster 0 on end

 	# Graphics
 	# TODO:
--- a/src/mainboard/up/squared/devicetree.cb
+++ b/src/mainboard/up/squared/devicetree.cb
@ -20,7 +20,6 @@ chip soc/intel/apollolake
 	# 0:HS400 (Default) 1:HS200 2:DDR50
 	register "emmc_host_max_speed" = "1"

-	device cpu_cluster 0 on end
 	device domain 0 on
 		subsystemid 0x8086 0x7270 inherit
 		device pci 00.0 on end	# - Host Bridge
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@ -1,4 +1,5 @@
 chip soc/intel/apollolake
+	device cpu_cluster 0 on end
 	device domain 0 on
 		device pci 00.0 alias system_agent	on	end # Host Bridge
 		device pci 00.1 alias dptf		on	end # DPTF
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@ -1,4 +1,5 @@
 chip soc/intel/apollolake
+	device cpu_cluster 0 on end
 	device domain 0 on
 		device pci 00.0 alias system_agent	on	end # Host Bridge
 		device pci 00.1 alias dptf		on	end # DPTF