security/tpm: Move tpm TSS and TSPI layer to security section

* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes

Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/intel/baytrail/romstage/romstage.c

@@ -30,7 +30,7 @@
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>

src/soc/intel/braswell/romstage/romstage.c

@@ -43,7 +43,7 @@
 #include <soc/romstage.h>
 #include <soc/smm.h>
 #include <soc/spi.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 void program_base_addresses(void)
 {

src/soc/intel/broadwell/romstage/romstage.c

@@ -25,7 +25,7 @@
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
 #include <elog.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <stage_cache.h>

src/soc/intel/common/tpm_tis.c

@@ -14,7 +14,7 @@
  */
 
 #include <arch/acpi.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 int tis_plat_irq_status(void)
 {