From 632ae13fe0ea459b29d10c25d23d89cfca20e3b7 Mon Sep 17 00:00:00 2001
From: "joel.bueno" <joel.bueno@openchip.com>
Date: Mon, 24 Feb 2025 19:01:59 +0100
Subject: [PATCH] soc/riscv/ucb: Switch to FDT parsing to get memory size
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Currently, coreboot tries to manually probe the memory for
the Spike target as part of the SOC_UCB_RISCV target.

However, Spike already passes a pointer to the device tree,
so use it instead to get the memory size (like qemu-riscv does).

TEST=Compile for SPIKE-RISCV and run (cmdline: spike -m1024 build/coreboot.elf)

Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43
Signed-off-by: joel.bueno <joel.bueno@openchip.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86588
Reviewed-by: Carlos López <carlos.lopezr4096@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/ucb/riscv/Kconfig |  1 +
 src/soc/ucb/riscv/cbmem.c | 10 +++++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig
index bd0945e908..e8a8d376ba 100644
--- a/src/soc/ucb/riscv/Kconfig
+++ b/src/soc/ucb/riscv/Kconfig
@@ -9,6 +9,7 @@ config SOC_UCB_RISCV
 	select ARCH_ROMSTAGE_RISCV
 	select ARCH_RAMSTAGE_RISCV
 	select RISCV_USE_ARCH_TIMER
+	select FLATTENED_DEVICE_TREE
 	bool
 	default n
 
diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c
index 5c423a05bb..ff3f5db3fc 100644
--- a/src/soc/ucb/riscv/cbmem.c
+++ b/src/soc/ucb/riscv/cbmem.c
@@ -1,10 +1,18 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <cbmem.h>
 #include <symbols.h>
 #include <ramdetect.h>
+#include <commonlib/device_tree.h>
+#include <mcall.h>
 
 uintptr_t cbmem_top_chipset(void)
 {
-	return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
+	uint64_t top;
+
+	top = fdt_get_memory_top((void *)HLS()->fdt);
+	ASSERT_MSG(top, "Failed reading memory range from FDT");
+
+	return MIN(top, (uint64_t)4 * GiB - 1);
 }