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nb/intel/pineview: Move to early cbmem

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TESTED on D510MO.

Change-Id: I05aa40df0d2a090fcf734416669e9e1bbff094e4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19414
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans 2017-04-21 15:54:44 +02:00 • committed by Martin Roth
commit 62e784bd8a
6 changed files with 61 additions and 6 deletions
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14
src/mainboard/intel/d510mo/romstage.c
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@ -31,6 +31,8 @@
#include <superio/winbond/common/winbond.h>
#include <lib.h>
#include <arch/stages.h>
#include <cbmem.h>
#include <romstage_handoff.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
#define SUPERIO_DEV PNP_DEV(0x4e, 0)
@ -99,6 +101,8 @@ static void rcba_config(void)
void mainboard_romstage_entry(unsigned long bist)
{
const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
int cbmem_was_initted;
int s3resume = 0;
if (bist == 0)
enable_lapic();
@ -131,4 +135,14 @@ void mainboard_romstage_entry(unsigned long bist)
ram_check(0x200000,0x300000);
rcba_config();
cbmem_was_initted = !cbmem_recovery(s3resume);
if (!cbmem_was_initted && s3resume) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
halt();
}
romstage_handoff_init(s3resume);
}