From 62c2b83937b91ee5e445bf40996b1761079ff031 Mon Sep 17 00:00:00 2001 From: Dennis Wassenberg Date: Wed, 2 Nov 2016 08:12:52 +0100 Subject: [PATCH] UPSTREAM: nb/intel/sandybridge: Lock PAVPC This makes CHIPSEC happy. We don't enable PAVP, but it shouldn't hurt to lock it nevertheless. BUG=None BRANCH=None TEST=None Signed-off-by: Dennis Wassenberg Reviewed-on: https://review.coreboot.org/17352 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Ronald G. Minnich Change-Id: I9428f0b6e8868832eb79f7aea24cbc7961c2aa8f Reviewed-on: https://chromium-review.googlesource.com/418370 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/northbridge/intel/sandybridge/finalize.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 93f62611b0..21bf9da332 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -23,6 +23,7 @@ void intel_sandybridge_finalize_smm(void) { pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config16(PCI_DEV_SNB, 0x58, 1 << 2); /* PAVP Lock */ pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */